TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 182

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

14.3.3 Transfer modes
14.3.2.3 Transmit/receive mode
14.3.3.1 Transmit mode
Transmit, receive and transmit/receive mode are selected by using SIO1CR<SIOM>.
(2)
(1)
(2)
(1)
Transmit mode is selected by writing “00B” to SIO1CR<SIOM>.
received sequentially beginning with the least significant bit (Bit0).
data is transferred sequentially beginning with the most significant bit (Bit7) and the data is received
sequentially beginning with the most significant (Bit7).
data is transferred sequentially beginning with the least significant bit (Bit0) and the data is received
sequentially beginning with the least significant (Bit0).
SIO1CR<SCK>. Transfer direction is selected by using SIO1CR<SIODIR>.
cleared to “0”.
SCK1
SIO1CR<SIODIR>, synchronizing with the
clock falling edge.
transferred to shift register, then the INTSIO1 interrupt request is generated, synchronizing with the
next falling edge on
LSB receive mode
LSB receive mode is selected by setting SIO1CR<SIODIR> to “1”, in which case the data is
MSB transmit/receive mode
MSB transmit/receive mode are selected by setting SIO1CR<SIODIR> to “0” in which case the
LSB transmit/receive mode
LSB transmit/receive mode are selected by setting SIO1CR<SIODIR> to “1”, in which case the
Starting the transmit operation
Transmit mode is selected by setting “00B” to SIO1CR<SIOM>. Serial clock is selected by using
When a transmit data is written to the transmit buffer register (SIO1TDB), SIO1SR<TXF> is
After SIO1CR<SIOS> is set to “1”, SIO1SR<SIOF> is set synchronously to “1” the falling edge of
The data is transferred sequentially starting from SO1 pin with the direction of the bit specified by
SIO1SR<SEF> is kept in high level, between the first clock falling edge of
SIO1SR<TXF> is set to “1” at the rising edge of pin after the data written to the SIO1TDB is
Note 1: In internal clock operation, when SIO1CR<SIOS> is set to "1", transfer mode does not start with-
Note 2: In internal clock operation, when the SIO1CR<SIOS> is set to "1", SIO1TDB is transferred to
Note 3: In external clock operation, when the falling edge is input from
pin.
out writing a transmit data to the transmit buffer register (SIO1TDB).
shift register after maximum 1-cycle of serial clock frequency, then a serial clock is output from
SCK1
set to "1", SIO1TDB is transferred to shift register immediately.
pin.
SCK1
pin.
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SCK1
pin's falling edge.
SCK1
pin after SIO1CR<SIOS> is
SCK1
TMP86PM49UG
pin and eighth