TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 188

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

14.3.3.3 Transmit/receive mode
SIO1CR<SIOS>
SIO1SR<SIOF>
SIO1SR<SEF>
SCK1
SI1 pin
SIO1SR<RXF>
SIO1SR<RXERR>
INTSIO1
interrupt
request
SIO1RDB
pin
(1)
The transmit/receive mode are selected by writing “10” to SIO1CR<SIOM>.
by using SIO1CR<SCK>. Transfer direction is selected by using SIO1CR<SIODIR>.
cleared to “0”.
SCK1
SIO1CR<SIODIR>, synchronizing with the
starts with the direction of the bit specified by SIO1CR<SIODIR>, synchronizing with the
pin's rising edge.
clock falling edge.
transferred to shift register. When 8-bit data has been received, the received data is transferred to
SIO1RDB from shift register, then the INTSIO1 interrupt request occurs, synchronizing with setting
SIO1SR<RXF> to “1”.
Note: If receive error is not corrected, an interrupt request does not generate after the error occurs.
Starting the transmit/receive operation
Transmit/receive mode is selected by writing “10B” to SIO1CR<SIOM>. Serial clock is selected
When a transmit data is written to the transmit buffer register (SIO1TDB), SIO1SR<TXF> is
After SIO1CR<SIOS> is set to “1”, SIO1SR<SIOF> is set synchronously to the falling edge of
The data is transferred sequentially starting from SO1 pin with the direction of the bit specified by
SIO1SR<SEF> is kept in high level between the first clock falling edge of
SIO1SR<TXF> is set to “1” at the rising edge of
Note 1: In internal clock operation, when the SIO1CR<SIOS> is set to "1", SIO1TDB is transferred to
Note 2: In external clock operation, when the falling edge is input from
Figure 14-12 Example of Receive Error Processing
pin.
shift register after maximum 1-cycle of serial clock frequency, then a serial clock is output from
SCK1
set to "1", SIO1TDB is transferred to shift register immediately. When the rising edge is input
from
A7 A6
SCK1
pin.
Start shift
operation
pin, receive operation also starts.
A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
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A
Start shift
operation
SCK1
Writing transmit
data A
SCK1
pin's falling edge. And receiving operation also
pin after the data written to the SIO1TDB is
B
Start shift
operation
Writing transmit
data B
SCK1
pin after SIO1CR<SIOS> is
Write a "0" after reading the
received data when a receive
error occurs.
SCK1
TMP86PM49UG
pin and eighth
SCK1