TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 183

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

14.3 Function
SIO1SR<SEF>
SO1 pin
SIO1SR<TXF>
SIO1CR<SIOS>
SIO1SR<SIOF>
SCK1 pin outout
INTSIO1
interrupt
request
SIO1TDB
(2)
(3)
Figure 14-6 Example of Internal Clock and MSB Transmit Mode
Writing transmit
data A
stops to “H” level by an automatic-wait function when all of the bit set in the SIO1TDB has been
transmitted. Automatic-wait function is released by writing a transmit data to SIO1TDB. Then, trans-
mit operation is restarted after maximum 1-cycle of serial clock.
SIO1SR<TXF> “1”, the next data is continuously transferred after transmission of previous data.
SIO1TDB before the shift operation of the next data begins.
tion is started. Then, INTSIO1 interrupt request is generated after SIO1SR<TXERR> is set to “1”.
During the transmit operation
When data is written to SIO1TDB, SIO1SR<TXF> is cleared to “0”.
In internal clock operation, in case a next transmit data is not written to SIO1TDB, the serial clock
When the next data is written to the SIO1TDB before termination of previous 8-bit data with
In external clock operation, after SIO1SR<TXF> is set to “1”, the transmit data must be written to
If the transmit data is not written to SIO1TDB, transmit error occurs immediately after shift opera-
Stopping the transmit operation
There are two ways for stopping transmits operation.
A
• The way of clearing SIO1CR<SIOS>.
• The way of setting SIO1CR<SIOINH>.
When SIO1CR<SIOS> is cleared to “0”, transmit operation is stopped after all transfer of the
data is finished. When transmit operation is finished, SIO1SR<SIOF> is cleared to “0” and
SO1 pin is kept in high level.
In external clock operation, SIO1CR<SIOS> must be cleared to “0” before SIO1SR<SEF> is
set to “1” by beginning next transfer.
Transmit operation is stopped immediately after SIO1CR<SIOINH> is set to “1”. In this
case, SIO1CR<SIOS>, SIO1SR register, SIO1RDB register and SIO1TDB register are ini-
tialized.
A7
Writing transmit
data B
A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1
Start shift
operation
B
Page 166
Start shift
operation
B0
Automatic wait
Writing transmit
data C
C
C7
Start shift
operation
C6 C5 C4 C3 C2 C1 C0
Clearing SIOS
TMP86PM49UG