TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 39

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TMP86xy49UG/F/NG

Manufacturer Part Number
TMP86xy49UG/F/NG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP86xy49UG/F/NG

Package
LQFP64/QFP64/SDIP64
Rom Types (m=mask,p=otp,f=flash)
M/P/F
Rom Size
16/32/60
Ram Size
512/1K/2K
Driver Led
13
Driver Lcd
-
Spi/sio Channels
2
Uart/sio Channels
2
I2c/sio Channels
1
High-speed Serial Output
-
Adc 8-bit Channels
-
Adc 10-bit Channels
16
Da Converter Channels
-
Timer Counter 18-bit Channel
-
Timer Counter 16-bit Channel
2
Timer Counter 8-bit Channel
4
Motor Channels
-
Watchdog Timer
Y
Dual Clock
Y
Clock Gear
-
Number Of I/o Ports
56
Power Supply (v)
4.5 to 5.5
2.2 System Clock Controller
2.2.4.2
interrupts. The following status is maintained during these modes.
IDLE1/2 mode and SLEEP1/2 mode
IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable
1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to
2. The data memory, CPU registers, program status word and port output latches are all held in the
3. The program counter holds the address 2 ahead of the instruction which starts these modes.
operate.
status in effect before these modes were entered.
Figure 2-10 IDLE1/2 and SLEEP1/2 Modes
release mode
Normal
“0”
No
Execution of the instruc-
IDLE1/2 and SLEEP1/2
modes start instruction
CPU and WDT are halted
tion which follows the
Starting IDLE1/2 and
SLEEP1/2 modes by
Interrupt processing
Interrupt request
Page 22
Reset input
instruction
IMF
Yes
No
“1” (Interrupt release mode)
Yes
Reset
TMP86PM49UG

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