TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 223

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

16.6 Data Transfer of I2C Bus
SCL pin
SDA pin
PIN
INTSBI
interrupt request
Write to SBIDBR
SCL pin
SDA pin
PIN
INTSBI
interrupt request
16.6.3.1 When the MST is “1” (Master mode)
(1)
(2)
Check the TRX and determine whether the mode is a transmitter or receiver.
generate a stop condition (Described later) and terminate data transfer.
8 bits, set the BC, set the ACK to “1”, and write the transmitted data to the SBIDBR. After writing
the data, the PIN becomes “1”, a serial clock pulse is generated for transferring a next 1 word of data
from the SCL pin, and then the 1 word of data is transmitted. After the data is transmitted, and an
INTSBI interrupt request occurs. The PIN become “0” and the SCL pin is set to low level. If the data
to be transferred is more than one word in length, repeat the procedure from the LRB test above.
read the received data from the SBIDBR (Reading data is undefined immediately after a slave
address is sent). After the data is read, the PIN becomes “1”. A serial bus interface circuit outputs a
serial clock pulse to the SCL pin to transfer next 1-word of data and sets the SDA pin to “0” at the
acknowledge signal timing.
outputs a clock pulse for 1-word of data transfer and the acknowledge signal each time that received
data is read from the SBIDBR.
When the TRX is “1” (Transmitter mode)
Test the LRB. When the LRB is “1”, a receiver does not request data. Implement the process to
When the LRB is “0”, the receiver requests next data. When the next transmitted data is other than
When the TRX is “0” (Receiver mode)
When the next transmitted data is other than of 8 bits, set the BC again. Set the ACK to “1” and
An INTSBI interrupt request occurs and the PIN becomes “0”. Then a serial bus interface circuit
Figure 16-10 Example of when BC = “000”, ACK = “1”
Figure 16-11 Example of when BC = “000”, ACK = “1”
Read SBIDBR
D7
1
D7
1
D6
2
D6
2
D5
3
D5
3
D4
4
Page 206
D4
4
D3
5
D3
5
D2
6
D2
6
D1
7
D1
7
D0
8
D0
8
9
New D7
Acknowledge
signal to a
transmitter
9
TMP86PM49UG
Acknowledge
signal from a
receiver