TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 59

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

3.4 Software Interrupt (INTSW)
Example 2 :Restarting without returning interrupt
3.4 Software Interrupt (INTSW)
3.5 Undefined Instruction Interrupt (INTUNDEF)
3.6 Address Trap Interrupt (INTATRAP)
3.4.1 Address error detection
3.4.2 Debugging
is highest prioritized interrupt).
erated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable inter-
rupt is in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is
requested.
trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable interrupt is in process. Contemporary pro-
cess is broken and INTATRAP interrupt process starts, soon after it is requested.
Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW
Use the SWI instruction only for detection of the address error or for debugging.
Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is gen-
Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software interrupt
Fetching instruction from unauthorized area for instructions (Address trapped area) causes reset output or address
Note: The operating mode under address trapped, whether to be reset output or interrupt processing, is selected on
(In this case, PSW (Includes IMF) before interrupt acceptance is discarded.)
rupt can be accepted immediately after the interrupt return instruction is executed.
memory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is gener-
ated and an address error is detected. The address error detection range can be further expanded by writing
FFH to unused areas of the program memory. Address trap reset is generated in case that an instruction is
fetched from RAM, DBR or SFR areas.
address.
Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next inter-
Note 1: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return inter-
Note 2: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service
FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent
Debugging efficiency can be increased by placing the SWI instruction at the software break point setting
(SWI) does.
watchdog timer control register (WDTCR).
PINTxx:
rupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example
2).
task is performed but not the main task.
INC
INC
INC
(interrupt processing)
LD
JP
SP
SP
SP
EIRL, data
Restart Address
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;
;
; Set IMF to “1” or clear it to “0”
; Jump into restarting address
; Recover SP by 3
TMP86PM49UG