TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 83

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

6.2 Watchdog Timer Control
6.2 Watchdog Timer Control
6.2.1 Malfunction Detection Methods Using the Watchdog Timer
Example :Setting the watchdog timer detection time to 2
dog timer is automatically enabled after the reset release.
Within 3/4 of WDT
detection time
Within 3/4 of WDT
detection time
The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watch-
dog timer output is activated by the binary-counter overflow unless the binary counters are cleared. When
WDTCR1<WDTOUT> is set to “1” at this time, the reset request is generated and then internal hardware is
initialized. When WDTCR1<WDTOUT> is set to “0”, a watchdog timer interrupt (INTWDT) is generated.
mode, and automatically restarts (continues counting) when the STOP/IDLE/SLEEP mode is inactivated.
The CPU malfunction is detected, as shown below.
If the CPU malfunctions such as endless loops or the deadlock conditions occur for some reason, the watch-
The watchdog timer temporarily stops counting in the STOP mode including the warm-up or IDLE/SLEEP
Note:The watchdog timer consists of an internal divider and a two-stage binary counter. When the clear code 4EH
1. Set the detection time, select the output, and clear the binary counter.
2. Clear the binary counter repeatedly within the specified detection time.
is written, only the binary counter is cleared, but not the internal divider. The minimum binary-counter overflow
time, that depends on the timing at which the clear code (4EH) is written to the WDTCR2 register, may be 3/
4 of the time set in WDTCR1<WDTT>. Therefore, write the clear code using a cycle shorter than 3/4 of the
time set to WDTCR1<WDTT>.
LD
LD
LD
LD
LD
:
:
:
:
(WDTCR2), 4EH
(WDTCR1), 00001101B
(WDTCR2), 4EH
(WDTCR2), 4EH
(WDTCR2), 4EH
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: Clears the binary counters.
: WDTT
: Clears the binary counters (always clears immediately before and
: Clears the binary counters.
: Clears the binary counters.
21
after changing WDTT).
/fc [s], and resetting the CPU malfunction detection
←
10, WDTOUT
←
1
TMP86PM49UG