TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 221

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

16.5 I2C Bus Control
16.5.11Slave address match detection monitor
16.5.12GENERAL CALL detection monitor
16.5.13Last received bit monitor
Master A
Master B
Accessed to SBIDBR or SBICRB
INTSBI
mode. Thus, the serial bus interface circuit stops output of clock pulses during data transfer after the AL is set
to “1”.
the SBICRB.
the received data matches the slave address setting by I2CAR with an address recognition mode (ALS = 0).
receiving the first 1-word of data.
tion in a slave mode. The AD0 is cleared to “0” when a start or stop condition is detected on a bus.
acknowledge mode, immediately after an INTSBI interrupt request is generated, an acknowledge signal is read
by reading the contents of the LRB.
Figure 16-8 Example of when a Serial Bus Interface Circuit is a Master B
When the AL is set to “1”, the MST and TRX are cleared to “0” and the mode is switched to a slave receiver
The AL is cleared to “0” by writing data to the SBIDBR, reading data from the SBIDBR or writing data to
In the slave mode, the AAS (Bit2 in SBISRB) is set to “1” when the received data is “GENERAL CALL” or
When a serial bus interface circuit operates in the free data format (ALS = 1), the AAS is set to “1” after
The AAS is cleared to “0” by writing data to the SBIDBR or reading data from the SBIDBR.
The AD0 (Bit1 in SBISRB) is set to “1” when all 8-bit received data is “0” immediately after a start condi-
The SDA line value stored at the rising edge of the SCL line is set to the LRB (Bit0 in SBISRB). In the
AL
MST
TRX
SCL pin
SDA pin
SCL pin
SDA pin
D7B D6B
D7A D6A D5A D4A
1
1
2
2
3
3
Releasing SDA pin and SCL pin to high level as losing arbitration.
4
4
Stop clock output
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D3A D2A D1A
5
5
6
6
7
7
D0A
8
8
9
9
D7A’
1
D6A’
2
TMP86PM49UG
D5A’
3