PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 766

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
If the AA flag is cleared and the IIC-bus module is in the addressed slave transmitter
mode, state 0xC8 will be entered after the last serial bit is transmitted. The IIC
module leaves state 0xC8, enters the “not addressed” slave receiver mode, and the
SDA line remains at a high level. In state 0xC8, the AA flag can be set again for future
address recognition.
If the AA flag is cleared and the IIC module is in the “not addressed” slave mode, its
own slave address and the general call address are ignored. Consequently, no
acknowledge is returned, and a serial interrupt is not requested.
Thus, IIC module can be temporarily released from the I
monitored. While the IIC module is released from the bus, START and STOP
conditions are detected, and serial data is shifted in.
Address recognition can be resumed at any time by setting the AA flag. If the AA flag
is set when the part’s own slave address or the general call address has been partly
received, the address will be recognized at the end of the byte transmission.
Bit 6: EN Enable
Bit 5: STA Start bit
When the STA bit is set to enter a master mode, the IIC module hardware checks the
status of the I
free, the IIC module waits for a STOP condition (which will free the bus) and
generates a START condition after a delay of a low clock period in the internal serial
clock generator.
If STA is set while IIC module is already in master mode and one or more bytes are
transmitted or received, the IIC module transmits a repeated START condition. STA
may be set at any time. It may also be set when the IIC module is an addressed slave.
When the STA bit is reset, no START condition or repeated START condition will be
generated.
Bit 4: STO Stop bit
A write to IIC_CONTROL Register will not affect this bit. It must be written via
IIC_STOP Register. When the STO bit is set while IIC module is in a master mode, a
STOP condition is transmitted to the I
•
•
•
When EN is ‘0’, the SDA and SCL outputs are constantly at 1 level leading to a
high impedance state at the associated port lines SDA and SCL. The state of the
SDA and SCL input lines are ignored; IIC module is in the “not addressed” slave
state, and the STO bit in IIC_CONTROL is forced to ‘0’. No other bits are
affected. SDA and SCL port lines may be used as open drain I/O ports.
When EN is ‘1’, IIC module is enabled. The port latches associated to SDA and
SCL must be set to logic 1.
EN should not be used to temporarily release IIC module from the I
because when EN is reset, the I
to temporarily release the IIC module.
2
C bus and generates a START condition if the bus is free. If it is not
Rev. 4.0 — 03 December 2007
2
C bus status is lost. The AA flag should be used
2
C bus.
PNX15xx/952x Series
2
C bus while the bus status is
Chapter 25: I
© NXP B.V. 2007. All rights reserved.
2
2
C bus
C Interface
25-766