PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 259

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 8: Registers Description
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
2
1
0
Offset 0x04 0FDC
31:15
14
13
12
11:10
9
8:6
5
4
3
2
1
0
Offset 0x04 0FE0
This register represents the status of direct access to PCI-XIO and PCI slave events.
31:27
26
25
24
23
22
21
20
19
18
17
16
15
14
13:12
11
10
Symbol
clr_dma_r_mabort
clr_dma_r_tabor
Reserved
Reserved
set_dma_xio_ack_done
Reserved
set_dma_done
Reserved
set_dma_err
Reserved
set_dma_mstr_parity_er
r
set_dma_err_parity
Reserved
set_dma_r_mabort
set_dma_r_tabor
Reserved
Reserved
pcii_wr_err
pcii_rd_err
xio_wr_err
xio_rd_err
pcir_wr_err
pcir_rd_err
pwrstate_chg
Reserved
pci2_wr_err
pci2_rd_err
pci1_wr_err
pci1_rd_err
pci_xio_ack_done
Reserved
serr_seen
Reserved
DMA Interrupt Set
PCI Interrupt Status
Acces
s
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Rev. 4.0 — 03 December 2007
Description
Clear DMA Received Master Abort
Clear DMA Received Target Abort
Set Rising edge of xio_ack has been observed
Set DMA transaction completed
Set Non-Supported DMA command attempted or not enabled
Set DMA master set or observed parity error (PERR)
Set DMA Detected parity error (PERR)
Set DMA Received Master Abort
Set DMA Received Target Abort
Interrupt on PCI DTL initiator write error flag
Interrupt on PCI DTL initiator read error flag
Interrupt on XIO DTL target write error flag
Interrupt on XIO DTL target read error flag
Interrupt on mmio register DTL target write error flag
Interrupt on mmio register DTL target read error
Power management register has been changed
Interrupt on PCI2 DTL target write error flag
Interrupt on PCI2 DTL target read error flag
Interrupt on PCI1 DTL target write error flag
Interrupt on PCI1 DTL target read error flag
Rising edge of xio_ack has been observed
SERR observed on PCI bus
PNX15xx/952x Series
Chapter 7: PCI-XIO Module
© NXP B.V. 2007. All rights reserved.
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