PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 598

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 8: Memory Based Scaler (MBS) Registers
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
31:30
29:16
15
14
13
12:8
7:0
Offset 0x10 C104
31:27
26:16
15:11
10:0
Offset 0x10 C108
31:29
Symbol
PFU_BAMODE
Reserved
PFU_HFLIP
Reserved
PFU_ENDIAN
Reserved
PFU_IPFMT
Reserved
PFU_LSIZE
Reserved
PFU_LCOUNT
PFU_SIZE_C4 [2:0]
Source Window Size
Variable Format Register
Acces
s
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Value
Rev. 4.0 — 03 December 2007
…Continued
Description
Base address mode
Mirror input mode
Input format endian mode
Input formats
00 (hex) = YUV 4:2:0, semi-planar
03 (hex) = YUV 4:2:0, planar
08 (hex) = YUV 4:2:2, semi-planar
0B (hex) = YUV 4:2:2, planar
0F (hex) = RGB or YUV 4:4:4, planar
24 (hex) = 1-bit indexed
45 (hex) = 2-bit indexed
66 (hex) = 4-bit indexed
87 (hex) = 8-bit indexed
A0 (hex) = packed YUY2 4:2:2
A1 (hex) = packed UYVY 4:2:2
AC (hex) = 16-bit variable contents 4:4:4
E8 (hex) = 32-bit variable contents 4:2:2
EC (hex) = 32-bit variable contents 4:4:4
Line size
Defines size of input window
1 = one pixel
Remark: Internal buffer lines are only 1024 pixels. Horizontal
and vertical scaling need to be ordered such that the
intermediate result fits into 1024 pixels buffer lines.
Line count
Defines size of input window
1 = one line
Size component #4 (alpha or V)
Number of bits minus 1 (e.g. 7 = 8 bits per component)
00 = single set (e.g. progressive video source)
base 1-3 according to number of planes (plane 1-3)
01 = alternate sets each line (e.g. interlaced video source)
base 1-3, first line in, etc. (plane 1-3)
base 4-6, second line in, etc. (plane 1-3)
1x = reserved
0: normal
1: mirrored input
0: same as system endian mode
1: opposite of system endian mode
Chapter 19: Memory Based Scaler
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
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