PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 648

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 36: Drawing Engine Data Registers
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
Offset 0x04 F700—F7FF PatRamColor (256 bytes)
This address range allows write access to the pattern cache ram. It is only for full color patterns. A full color pattern consists
of 64 bytes of data at 8 bpp, 128 bytes at 16 bpp, and 256 bytes of data at 32 bpp. Full color patterns should be loaded
starting at address 0x1700. Patterns must be loaded sequentially because the lower order address bits are ignored as a
pattern is loaded.
Offset 0x05 0000
This address space receives host data for BLTs that require host data. All addresses in this range map to the host write
buffer. It allows the host to use REP MOVSD instructions to efficiently copy data from system memory to the BLT engine.
When doing a BLT that requires host data (host to screen), it is necessary to program SRC[1:0] in the BltCtl register to
select host data.
This register is byte accessible, but... Host-to-Screen BLTs always require an integer number of
from the host. Although the HostData port will accept byte writes to load individual bytes of data, writing the high byte
actually transfers the host data into the Engine. Reads from this register return unknown data but do not hang the bus.
Writing excess data to this register space is not recommended, but will not cause the bus to hang.
Symbol
—
FFFF Host Data (64 kB - Memory Space)
Acces
s
Value
Rev. 4.0 — 03 December 2007
Description
PNX15xx/952x Series
Chapter 20: 2D Drawing Engine
DWORD
© NXP B.V. 2007. All rights reserved.
s to be transferred
20-648