PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 516

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
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PNX15XX_PNX952X_SER_N_4
Product data sheet
2.7 Codec Control
Table 5: Example Setup For 64-Bit I
Remark: The transfer of data from SDRAM into the Audio Out module's transmit
FIFOs is initiated by the transition of WS, not by transmit enable. As a consequence,
there is a delay between the receipt of the first WS pulse and the transmission of the
first data. The length of this delay is dependent on system load and is not easily
predictable.
In addition to the left and right data fields that are generated based on autonomous
DMA action, a serial frame generated by Audio Out can be set to contain one or two
control fields of up to 16 bits in length. Each control field can be independently
enabled or disabled by the CC1_EN, CC2_EN bits in AO_CTL.
The content shifted into the frame is taken from the CC1 and CC2 field in the AO_CC
register. The CC1_POS and CC2_POS fields in the AO_CFC register determine the
first bit position in the frame where the control field is emitted observing the setting of
DATAMODE (i.e., LSB or MSB first).
The CC_BUSY bit in AO_STATUS indicates if the Audio Out unit is ready to receive
another CC1, CC2 value pair. Writing a new value pair to AO_CC writes the value into
a buffer register and raises the CC_BUSY status. (See
As soon as both CC1 and CC2 values have been copied to a shadow register in
preparation for transmission, CC_BUSY is negated, indicating that the Audio Out
logic is ready to accept a new codec control pair. The old CC1/CC2 data is
transmitted continuously (i.e., software is not required to provide new CC1 and CC2
data).
Software must ensure that the CC_BUSY status is negated before writing a new
CC1, CC2 pair. The user, by the process of waiting on CC_BUSY, can reliably emit a
sequence of individual audio frames with distinct control field values. This can, for
example, be used during codec initialization. Note that no provision is made for
interrupt-driven operation of such a sequence of control values. It is assumed, after
initialization, that the value of control fields determines slowly changing,
asynchronous parameters such as output volume.
Field
POLARITY
LEFTPOS
RIGHTPOS
DATAMODE
SSPOS
CLOCK_EDGE 0
WSDIV
WS_PULSE
Rev. 4.0 — 03 December 2007
Value Explanation
0
0
32
0
0
63
0
Frame starts with negative edge Audio Out WS.
LEFT[MSB] will go to serial frame position 0.
RIGHT[MSB] will go to serial frame position 32.
MSB first.
Stop with LEFT/RIGHT[0], send 0s after.
(For 32-bit/sample mode, this field could be set to 14 to ensure
zeroes in all unused bit positions.)
Audio Out SD change on negative edge Audio Out SCK
Serial frame length = 64
Emit 50% duty cycle Audio Out WS.
2
S Framing
PNX15xx/952x Series
Section 4. on page
Chapter 15: Audio Output
© NXP B.V. 2007. All rights reserved.
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