PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 734

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
5.12.5 Pattern Match Filtering and Logic Functions
The LAN100 has four pattern-matching filters. Each filter is capable of covering
64-byte window in any location specified by PatternMatchSkip0/1/2/3[10:0] registers.
The pattern match filters analyze received packets for certain patterns. If the filter
finds a match, the filter asserts its match signal. Depending on the Join function and
the “AndOr” relation with other filters, the packet is then accepted or rejected.
The pattern-matching filters are imperfect filters. They calculate a 32-bit CRC on a
64-byte window. The window can have an offset as specified by the associated
PatternMatchSkip register. The Skip register is 11 bits wide, allowing up to 2047
bytes at the start of the packet to be skipped. The PatternMatchMask registers
specify a mask for the pattern matching windows so that some bytes can be masked
out in the CRC calculation. A byte is only input in the CRC calculation if the
corresponding byte enable bit in the PatternMatchMask register is set. A pattern
match filter produces a match if the calculated CRC matches the CRC in the
associated PatternMatchCRC register. Each of the four pattern match filters is
enabled by setting the corresponding PatternMatchEn[3:0] bit in the RxFilter register
to 1.
The same 32-bit CRC and polynomial are used as with the standard Ethernet CRC.
The PatternMatchMask register is 64 bits long, allowing up to 64 consecutive bytes of
the received packet to be included in the CRC calculation. When bit b in the
PatternMatch register is 1 and the value of the Skip register is s , then receive packet
byte number ( s + b ) is included in the CRC calculation. Counting starts at the
destination address field of the Ethernet MAC frame. The PatternMatchMask register
is split into low-order and high-order parts, and registers PatternMatchMaskL and
PatternMatchMaskH are each 32 bits wide.
There are four separate pattern-matching filters supported, and there are 4 sets of
related registers (PatternMatchMaskL0/1/2/3, PatternMatchMaskH0/1/2/3,
PatternMatchCRC0/1/2/3, PatternMatchSkip0/1/2/3), one set for each filter.
The PatternMatchJoin register bits allow several of the pattern matches to be
combined together to implement a more complex combined check. This can be used
to create a pattern match of more than 64 bits, and the multiple pattern matches do
not need to check adjacent portions of the receive packet.
Section 3.3
For example, if the PatternMatchJoin register is set to 0xAFAFF0, then the results of
the pattern-match filter 0 and pattern-match filter 1 will be ANDed together, while the
results of filter 2 and 3 will be ignored. If the PatternMatchJoin register is set to
0x7A1BB1, then the join logic will perform the complex function:
where a , b , c , d are the results from the 0/1/2/3 filters.
A pattern match is enabled by setting the corresponding PatternMatchEn bit in the
RxFilterWOLControl register to 1. This can be done separately for each of the four
filters. If the system is in power-down mode, if a pattern match detects a wake-up
event, the corresponding PatternMatch bit in the RxFilterStatus register is set. If the
( a & ! b ) | c | ! d
defines the PatternMatchJoin register.
Rev. 4.0 — 03 December 2007
Chapter 23: LAN100 — Ethernet Media Access Controller
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
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