PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 106

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 9: PCI/XIO-16 Bus Interface Unit Capabilities
11. Endian Modes
PNX15XX_PNX952X_SER_N_4
Product data sheet
External Device
external DRAM
external Motorola
style masters
external 8/16-bit
XIO DMA devices
10.3.3 IDE Drive Interface
Device Type
not supported
not supported
not supported
10.4 10/100 Ethernet MAC
The PNX15xx/952x Series contains an IDE controller that uses some of the PCI pins
and a few sideband signals. Two external TTL devices are all that is required to
interface to an actual IDE cable/drive. The IDE controller capabilities are:
The PNX15xx/952x Series integrates a 10/100 Ethernet MAC sub-layer of the IEEE
802.3 standard enabling an external PHY to be attached through a Reduced Media
Independent Interface (RMII) or a standard Media Independent Interface (MII). It
implements dual transmit descriptor buffers, support for both real-time and non-real-
time traffic and support for quality of service (QoS) using low-priority and a high-
priority transmit queues. Among other features the 10/100 Ethernet MAC module
includes:
The MAC address is programmable into an MMIO register. The MAC address could
be located in an externally attached EEPROM.
PNX15xx/952x Series fully supports little- and big-endian software stacks.
PNX15xx/952x Series always starts in a fixed endian mode which is determined by
the boot script. There is a system provision for TM3260 software to reset and restart
the TM3260 in the opposite endian mode such that a field software Flash upgrade
can release a ‘endian mode opposite boot’ software upgrade.
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controls attached disks in PIO mode, for a peak data rate of 16.6 MB/s (PIO4)
supports sustained bandwidth of up to 10 MB/s
sends DMA blocks of disk data to and from system DRAM
all IDE registers are accessible to TM3260 software
Wake-on-LAN power management support. This allows system wake-up using
receive filters or a magic packet detection filter.
Receive filtering with perfect address matching, a hash table imperfect filter and 4
pattern match filters.
Memory traffic optimization via buffering and prefetching
Capabilities
not supported on PCI/XIO.
PNX15xx/952x Series PCI/XIO does NOT support external Motorola style
masters. PNX15xx/952x Series assumes that it is always the master over the
XIO bus.
not supported. Use one of the streaming DV inputs or outputs instead.
Rev. 4.0 — 03 December 2007
PNX15xx/952x Series
Chapter 2: Overview
© NXP B.V. 2007. All rights reserved.
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