PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 41

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 4: PNX1500 Interface
PNX15XX_PNX952X_SER_N_4
Product data sheet
Pin Name
GPIO06/CLOCK06
GPIO05/CLOCK05
GPIO04/CLOCK04
GPIO03/CLOCK03/
BOOT_MODE03
GPIO02/CLOCK02/
BOOT_MODE02
GPIO01/CLOCK01/
BOOT_MODE01
GPIO00/CLOCK00/
BOOT_MODE00
JTAG Interface (debug access port and 1149.1 boundary scan port)
JTAG_TDI
JTAG_TDO
JTAG_TCK
JTAG_TMS
Power Supplies and Ground
Refer to
for board level connection and decoupling associated with these pins.
VDDA
VSSA_1.2
VCCA[]
VSSA[]
VCCP[]
VCCM[]
Section 10. on page 1-74
BGA
Ball
C11
A10
D6
D5
B9
A8
A7
A4
A1
B1
A3
B3
B4
-
-
-
-
-
-
-
Pad
Type
BPX2T14MCP
BPTS1CHP
BPTS1CHP
BPTS1CHP
BPTS3CHP
BPTS1CHP
BPTS1CHP
BPTS1CHP
VDDE3V3
VDDE3V3
IPCHP
IPCHP
APOD
APOD
APOD
APOD
IPCP
-
-
-
Rev. 4.0 — 03 December 2007
I/O
Type
I/O/D
I/O/D
I/O/D
I/O/D
I/O/D
I/O/D
I/O/D
PWR
GND
PWR
GND
PWR
PWR
IN
IN
IN
O
-
-
-
GPIO
#
6
5
4
3
2
-
1
-
0
-
-
-
-
-
-
-
-
-
-
-
P Description
U
U
U
D After the power up and boot sequence, this pin
U
U
U
U JTAG Test Data Input.
U JTAG Test Clock Input.
U JTAG Test Mode Select Input.
-
-
-
- JTAG Test Data Output. This pin can either be an
- Analog, quiescent VDD. Refer to
- Analog, quiescent ground for the VDDA analog
- Analog, quiescent VCCP, 3.3 V. Refer to
- Analog, quiescent ground for the VCCA analog
- 3.3 V I/O power supply for peripherals I/Os. Refer to
- Power supply for the memory DDR-I I/Os (3.3 V
Used as GPIO pins. These pins can also be used to
output internally generated clocks for the external
components present on the board. These GPIO
pins can also be used as clocks for sampling or
pattern generation in the GPIO module
(Section 2.11.2 on page
GCLOCK05 requires a board level 27-33
resistor to reduce ringing.
functions as a GPIO[3] pin. This pin can also be
used as a clock for sampling or pattern generation
in the GPIO module. This GPIO pin may be
strapped with a resistor to VDD or VSS to
determine the PNX1500 boot mode upon reset.
After the power up and boot sequence, these pins
are configured as GPIO[2:0] pins. These pins can
also be used as clocks for sampling or pattern
generation in the GPIO module. These GPIO pins
may be strapped with resistors to VDD or VSS to
determine the PNX1500 boot mode upon reset.
output, or float. It is never an input.
board level connections.
supply. Refer to
connections.
for board level connections. Refer to
complete pin list.
supply. Refer to
connections. Refer to
Table 5
capable of ATE, not for functional operation). Refer
to
Table 5
for a complete pin list.
for a complete pin list.
PNX15xx/952x Series
Chapter 1: Integrated Circuit Data
Figure 27
Figure 26
Table 5
5-170). GPIO05/
for board level
for board level
for a complete pin list.
© NXP B.V. 2007. All rights reserved.
Figure 27
Table 5
Figure 26
for
series
for a
1-41