PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 579

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 6: SPDIF Input Registers
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
8
7
6
5
4
3
2
1
0
Offset 0x10 AFF4
31
30:0
The PWR_DWN register is provided for software use only. The PWR_DWN bit has no functionality internal to the SPDI Input
module. The bit is used to provide power control status for system software block power management. The default power on
state of this bit is logic ‘0’.
Offset 0x10 AFFC
31:16
15:12
11:8
7:0
The MODULE_ID register allows software identification of the SPDIF Input module. The values found in the MODULE_ID
register will change with each version of the SPDIF Input module.
Symbol
UCBITS_SET
LOCK_SET
VERR_SET
PERR_SET
OVR_SET
HBE_SET
BUF1_ACTIVE_SET
BUF2_FULL_SET
BUF1_FULL_SET
PWR_DWN
Unused
Module ID
MAJ_REV
MIN_REV
APERTURE
SPDI_PWR_DWN
SPDI_MODULE_ID
…Continued
Acces
s
W
W
W
W
W
W
W
W
W
R/W
R
R
R
R
Value
0
0
0
0
0
0
0
0
0
0
-
0x0110
0
0x1
0
Rev. 4.0 — 03 December 2007
Description
1 = UCBITS bit in SPDI_STATUS is to be set to logic ‘1’. Level
trigger interrupt will be raised to the external interrupt controller if
the corresponding enable bit is set to logic ‘1’. 0 = No effect
1 = LOCK bit in SPDI_STATUS is to be set to logic ‘1’. Level trigger
interrupt will be raised to the external interrupt controller if the
corresponding enable bit is set to logic ‘1’. 0 = No effect
1 = VERR bit in SPDI_STATUS is to be set to logic ‘1’. Level trigger
interrupt will be raised to the external interrupt controller if the
corresponding enable bit is set to logic ‘1’. 0 = No effect
1 = PERR bit in SPDI_STATUS is to be set to logic ‘1’. Level trigger
interrupt will be raised to the external interrupt controller if the
corresponding enable bit is set to logic ‘1’. 0 = No effect
1 = OVERRUN bit in SPDI_STATUS is to be set to logic ‘1’. Level
trigger interrupt will be raised to the external interrupt controller if
the corresponding enable bit is set to logic ‘1’. 0 = No effect
1 = HBE bit in SPDI_STATUS is to be set to logic ‘1’. Level trigger
interrupt will be raised to the external interrupt controller if the
corresponding enable bit is set to logic ‘1’. 0 = No effect
1 = BUF1_ACTIVE bit in SPDI_STATUS is to be set to logic ‘1’.
Level trigger interrupt will be raised to the external interrupt
controller if the corresponding enable bit is set to logic ‘1’. 0 = No
effect
1 = BUF2_FULL bit in SPDI_STATUS is to be set to logic ‘1’. Level
trigger interrupt will be raised to the external interrupt controller if
the corresponding enable bit is set to logic ‘1’. 0 = No effect
1 = BUF1_FULL bit in SPDI_STATUS is to be set to logic ‘1’. Level
trigger interrupt will be raised to the external interrupt controller if
the corresponding enable bit is set to logic ‘1’. 0 = No effect
The bit is used to provide power control status for system software
block power management.
This field identifies the block as type SPDIF Input.
SPDIF Input ID = 0x0110.
Major Revision ID
Minor Revision ID
Aperture size
PNX15xx/952x Series
Chapter 18: SPDIF Input
© NXP B.V. 2007. All rights reserved.
18-579