PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 520

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
3.1.2 Clock System Operation
Table 7
a bit clock of 64 Fs.
Table 7: Clock System Setting
The values of SCKDIV given assume the oversampling clock supplied to Audio Out is
either 256 Fs or 384 Fs. The value of SCKDIV is determined by
Remark: SCKDIV is in the range of 0-255.
Word Select (WS) and Serial Clock (SCK) are sent to the external D/A converter in
the master mode. WS determines the sample rate: each active channel receives one
sample for each WS period. SCK is the data bit clock. The number of SCK clocks in a
WS period is the number of data bits in a serial frame required by the attached D/A
converter.
WS is derived from the SCK bit clock. It is controlled by the value of WSDIV and it
sets the serial frame length. The number of bits per frame is equal to WSDIV+1.
There are some minimum length requirements for a serial frame. Refer to
Section 2.6.1 on page 15-515
SCK and WS can be configured as input or output by the SER_MASTER control field
in the AO_SERIAL register. If configured as an output, SCK can be set to a divider of
the OSCLK output frequency. (See
Whether set as input or output, the SCK connector is always used as the bit clock for
parallel to serial conversion. The WS signal always acts as the trigger to start the
generation of a serial frame. WS can also be programmed using WSDIV to control
the serial frame length. The number of bits per frame is equal to WSDIV+1.
If the serial frame length is set to be an odd number of bits and the WS pulse is
programmed to be 50% duty cycle, the portion of the WS waveform that is in the low
state will have the extra clock bit.
The preferred configuration of the clock system options is to use OSCLK as the D/A
subsystem master clock and let the D/A subsystem be a timing slave to the serial
interface (SER_MASTER = 1).
Some D/A converters provide somewhat better SNR properties if they are configured
as serial masters, so the Audio Out should be configured as a slave in this case
(SER_MASTER = 0). As illustrated by
converter that constructs the serial frame is indifferent as to who is the serial master.
f SCK
Fs
44.1 kHz
48.0 kHz
44.1 kHz
48.0 kHz
=
--------------------------------- -
SCKDIV
presents several sample rates with the SCKDIV setting necessary to achieve
f OSCLK
+
Rev. 4.0 — 03 December 2007
1
OSCLK
256 Fs
256 Fs
384 Fs
384 Fs
for details.
Section 4. on page 15-522
Figure
6, the internal parallel to serial
SCKDIV
3
3
5
5
PNX15xx/952x Series
Chapter 15: Audio Output
for more details.)
Equation
© NXP B.V. 2007. All rights reserved.
SCK
64 Fs
64 Fs
64 Fs
64 Fs
11.
15-520
(11)