PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 633

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 10: Pixel Size
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
Offset 0x04 F408
31:16
15:8
7:0
Symbol
Reserved
PFormat[7:0]
Depth[5:0]
Pixel Size
This register specifies the pixel size and format for the drawing engine for BLTs and
vectors. This register is unchanged by any drawing operations.
The
Note that in the 4534 case, the format name is not indicative of the actual order of the
bits.
Table 11: Pixel Format Bit Assignments
The YUV values have ranges which match the D1 format in the CCIR 656. Y is an
unsigned value ranging from 16 to 235. U and V are signed offset values ranging from
16 to 240, where 128 represents the zero point.
Format
RGB 565
RGB 4534
RGB 4444
RGB 8888
VYU 8888
YUV 8888
Acces
s
R/W
R/W
Table 11
Value
3
08
shows the pixel bit assignments for each of the six color formats above.
Rev. 4.0 — 03 December 2007
31
aaaaaaaa
aaaaaaaa
aaaaaaaa
Description
Currently used only during Alpha-Blending operations. The format is
dependent on the color depth. Refer to
assignments.
16 bpp:
0000_0000RGB 565
0000_0001 RGB 4444
0000_0010RGB 4534
0000_1000RGB 565 dithered
0000_1001 RGB 4444 dithered
0000_1010RGB 4534 dithered
32 bpp:
0000_0000 RGB 8888
0000_0001 VYU 8888
0000_0010 YUV 8888
Note: Specifying any other combination of bits will result in an
invalid command being executed.
Specifies the number of bits per pixel.
00100000b32 bpp
00010000b16 bpp
00001000b8 bpp
All other values are reserved.
24
23
RRRRRRRR
VVVVVVVV
YYYYYYYY
16
PNX15xx/952x Series
Chapter 20: 2D Drawing Engine
15
RRRRRGGG
aaaaRRRR
aaaaRRRR
GGGGGGGG
YYYYYYYY
UUUUUUUU
8
Table 11
© NXP B.V. 2007. All rights reserved.
below for bit
7
GGGBBBBB
GGGGBBBB
GGGGGBBB
BBBBBBBB
UUUUUUUU
VVVVVVVV
0
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