PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 15

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Chapter 6: Boot Module
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Chapter 7: PCI-XIO Module
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Chapter 8: General Purpose Input Output Pins
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Chapter 9: DDR Controller
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Chapter 10: LCD Controller
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Chapter 11: QVCP
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PNX15XX_PNX952X_SER_N_4
Product data sheet
Boot Block Diagram
System Memory Map and Block Diagram Con-
figuration for PNX15xx/952x Series in Standa-
lone Mode
PCI-XIO Block Diagram
Read Status
Read Data
Write Data
Block Erase
Motorola Write With DSACK
Motorola Write Without DSACK
Motorola Read
GPIO Module Block Diagram
Functional Block Diagram of a GPIO Pin
32-bit Timestamp Format
1-bit Signal Sampling
Up to 4-bit Signal Sampling
1-bit Pattern Generation
The two MTL Ports of the DDR SDRAM Con-
troller
Arbitration in the DDR Controller
CPU account
Arbitration when DMA has priority
CPU account using dynamic ratios
Address Mapping: Interleaved Mode
DDR SDRAM Controller Start and Halt State
Machine
Examples of Supported Memory Configura-
Block diagram of the LCD Controller
Generic Power Sequence for TFT LCD Panels
346
QVCP Top Level Diagram
QVCP BLock Diagram
Undithering and Pedestal Manipulation
315
327
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Rev. 4.0 — 03 December 2007
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PNX15xx/952x Series
System Memory Map and Block Diagram Con-
figuration for PNX15xx/952x Series in Host-
assisted Mode
NOR Flash Write
NOR Flash Read
IDE Interface
Isolation Translation Logic
Register Transfer/PIO Data Transfer on IDE
235
Timings on IDE Bus
IDE Transaction, Flow Controlled by Device
IORDY
Up to 4-bit Samples per FIFO in Pattern Gen-
eration Mode
Example of Ir TX Signals with and without
Sub-Carrier
IrDA Control TX with Sub-Carrier Enabled
Sub-Carrier Multiplexing for TX
Examples of Duty Cycles for Ir TX Signals
tions
Tcas Timing Parameter
Trrd and Trc Timing Parameters
Trfc Timing Parameter
Twr Timing Parameter
Tras Timing Parameter
Trp Timing Parameter
Trcd_rd Timing Parameter
Trcd_wr Timing Parameter
Power Sequencing State Machine Block Dia-
gram
Clock Gating Logic
4:2:2 and 4:4:4 Formats
Mixer Block Diagram—Pixel Selection
Mixer Block Diagram—Pixel Processing
329
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Connected Media Processor
280
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© NXP B.V. 2007. All rights reserved.
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