PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 237

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
4. Application Notes
PNX15XX_PNX952X_SER_N_4
Product data sheet
4.1 DTL Interface
4.2 System Memory Bus Interface, the MTL Bus
The DTL side of the PCI module,
It supports both big and little-endian systems.
Features:
To optimize PCI-to-system memory throughput in the PNX15xx/952x Series system,
a direct path is provided between PCI and the system memory bus using the MTL
interface.
Features:
The memory interface has two registers that allow the interface to be tuned for
optimum performance. A slave tuning register allows the user to select how much
data will be prefetched from memory during reads. For mem_read commands,
anywhere from 2 to 32 32-bit words may be selected. For mem_read_line commands,
one cache line will be prefetched. And for mem_read_multiple, anywhere from 8 to
1024 32-bit words may be prefetched. A threshold is used to determine when
additional data should be requested. This must be set to a value smaller then the
smallest of the 3 prefetch sizes of the various read memory command types. Note
that the cache line size must be set to a non-zero value before using cache line read
commands.
The DMA read channel also has a prefetch size and threshold register. Improper
settings of these registers combined with improper command type can result in an
external master being starved for data. An example of this is when 2 masters are both
attempting to do reads from the PCI.
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Dedicated port for MMIO register access
Dedicated port for direct access to XIO devices
Dedicated port for PCI memory space
Second PCI port which may be configured to access PCI memory or IO space
Each port may be configured for posted or non-posted writes.
Bursting to internal MMIO register space is not supported.
The 2 PCI targets support “retry” on PCI for reads and non-posted single writes.
For PCI burst reads, speculative read of user-selectable number of words is done
from the memory.
Two read and two write channels
Continuous PCI write/read bursts can be sustained (contingent on availability of
data on the DVP memory bus).
Rev. 4.0 — 03 December 2007
Figure
1, consists of a single initiator and 4 targets.
PNX15xx/952x Series
Chapter 7: PCI-XIO Module
© NXP B.V. 2007. All rights reserved.
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