PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 195

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 11: CLOCK MODULE REGISTERS
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
31:3
2
1
0
Offset 0x04,7308
31:4
3
2:1
0
Offset 0x04,730C
31:3
2
1
0
Offset 0x04,7310
31:4
3
2:1
0
Offset 0x04,7314
31:5
Symbol
Reserved
turn_off_ack
sel_clk_ai_sck
en_clk_ai_sck
Reserved
turn_off_ack
sel_ao_osclk
en_ao_osclk
Reserved
turn_off_ack
sel_clk_ao_sck
en_clk_ao_sck
Reserved
turn_off_ack
sel_clk_spdo
en_clk_spdo
Reserved
CLK_AO_OSCLK
CLK_AO_SCK_CTL
CLK_SPDO_CTL
CLK_SPDI_CTL
Acces
s
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
…Continued
Value
-
0
0
1
-
0
00
1
-
0
0
1
-
0
00
1
-
Rev. 4.0 — 03 December 2007
Description
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
0: clk_ai_sck = 27 MHz xtal_clk
1: clk_ai_sck = AI_SCK pin
1: enable clk_ai_sck
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
00: ao_osclk = 27 MHz xtal_clk
01: ao_osclk = DDS3
10: ao_osclk = PLL1
11: ao_osclk = XIO_D[14]
1: enable clk_ao_osclk
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
0: clk_ao_sck = 27 MHz xtal_clk
1: clk_ao_sck = AO_SCK pin
1: enable clk_ao_sck
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
00: clk_spdo = 27 MHz xtal_clk
01: clk_spdo = DDS5
10: clk_spdo = 27 MHz xtal_clk
11: clk_spdo = XIO_D[15]
1: enable clk_spdo
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
PNX15xx/952x Series
Chapter 5: The Clock Module
© NXP B.V. 2007. All rights reserved.
5-195