PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 501

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
4. Register Descriptions
Table 2: Register Summary
Table 3: Fast general purpose INput (FGPI)
PNX15XX_PNX952X_SER_N_4
Product data sheet
Offset
0x07,0000
0x07,0004
0x07,0008
0x07,000C
0x07,0010
0x07,0014
0x07,0018
0x07,001C
0x07,0020
0x07,0024
0x07,0028 -
0x07,0FDC
0x07,0FE0
0x07,0FE4
0x07,0FE8
0x07,0FEC
0x07,0FF0
0x07,0FF4
0x07,0FF8
0x07,0FFC
Bit
FPGI Registers
Offset 0x07,0000
31:15
14
13
Symbol
Reserved
POLARITY_CLK
CAPTURE_ENABLE_2
Name
FGPI_CTL
FGPI_BASE1
FGPI_BASE2
FGPI_SIZE
FGPI_REC_SIZE
FGPI_STRIDE
FGPI_NREC1
FGPI_NREC2
FGPI_THRESH1
FGPI_THRESH2
reserved
FGPI_IR_STATUS
FGPI_IR_ENA
FGPI_IR_CLR
FGPI_IR_SET
FGPI_SOFT_RST
FGPI_IF_DIS
FGPI_MOD_ID_EXT
FGPI_MOD_ID
4.1 Mode Registers
FGPI_CTL
Acces
s
R
R/W
R/W
Clock
Domain
fgpi
mmio
mmio
fgpi
fgpi
fgpi
mmio
mmio
fgpi
fgpi
n/a
mmio
mmio
mmio
mmio
mmio
mmio
mmio
mmio
Value
0
0
0
Rev. 4.0 — 03 December 2007
Description
Controls operational mode and enables/disables DMA transfers
Starting address for first buffer
Starting address for second buffer
Number of records/messages per buffer
Size of record/message in samples
Address stride between records/messages
Number of records/messages transferred into buffer 1
Number of records/messages transferred into buffer 2
Interrupt Threshold for Buffer 1
Interrupt Threshold for Buffer 2
Module Interrupt Status
Module Interrupt Enables
Module Interrupt Clear (Interrupt Acknowledge)
Module Interrupt Set (Debug)
Module Software Reset
Module Interface Disable
Module ID Extension
Module ID
Description
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Externally selects active clock edge for clk_fgpi via fgpi_clk_pol
Note: This bit not used in the PNX15xx/952x Series. All FGPI clock
control is in the clock module.
Enable input capture into buffer 2. This bit, along with bit 12 below,
start and stop FGPI DMA activity.
0 = rising edge
1 = falling edge
Chapter 14: FGPI: Fast General Purpose Interface
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
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