PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 331

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
2) Select the minimum (min) window size allowed; 20 or 40 are good examples.
Higher minimum values increase the latency, but can also slightly increase the DDR
efficiency (because more requests of one type (DMA or CPU) are handled in
sequence). The value 20 is based on a 128-byte transfer that takes 16 data transfer
cycles on a 32-bit DDR interface. Assuming an average DDR efficiency of 80% a total
of 20 cycles will be needed to start and finish this transfer.
3) Use the minimum window value for the port with the least traffic (DMA or CPU) and
calculate the other window according to the following formula:
if (hrt_pk < cpu)
hrt_window = min;
cpu_window = ((tot_bw / hrt_pk) -1)* hrt_window;
else
cpu_window = min;
hrt_window = (hrt_pk / (tot_bw - hrt_pk)) * cpu_window;
endif
4) If the selected minimum value is low and the calculated window size is much
bigger than the minimum value, setting ‘always’ pre-empt (0x3) on the high bandwidth
traffic (and maybe even ‘never’ pre-empt (0x0) on the low bandwidth traffic) will be
needed to make sure the low bandwidth modules get enough traffic.
5) The next parameter to calculate is cpu_ratio. To do this, first account for the fact
that normally not all available bandwidth will be used. It is a good idea to distribute the
headroom proportionally between the CPU and the soft real time DMA, as shown in
the following formulas:
srt2 = (tot_bw - hrt_avg) * srt / (srt + cpu);
cpu2 = (tot_bw - hrt_avg) * cpu / (srt + cpu);
6) The cpu_ratio and cpu_limit make sure that when the CPU is asking too much
bandwidth that it gets blocked out in the CPU window and soft real time DMA is
allowed access instead. The cpu_ratio determines how many cycles the CPU gets
blocked (versus the DMA) for each cycle the DDR spends on CPU data transfers. The
cpu_ratio is added to the account for each DDR burst, a DDR burst length is 4 cycles.
So the formula for cpu_ratio is:
cpu_ratio = 4 * (hrt_avg + srt2) / cpu2;
7) Finally the cpu_limit needs to be estimated, as it basically determines how many
consecutive CPU transfers are allowed to finish before the CPU gets blocked out. A
typical value is one data cache line replacement (copy back and fetch) and one
instruction fetch. Assuming a data and instruction cache line size of 64 bytes, that is a
total of 3*64 = 192 bytes.
For each DDR burst (4 clock cycles) the DDR transfers (for a dual data rate, 32-bit
DDR interface) 4*2*4=32 bytes, so 192/32 = 6 bursts are needed. The cpu_limit
needs to be at least 6*cpu_ratio.
Rev. 4.0 — 03 December 2007
PNX15xx/952x Series
Chapter 9: DDR Controller
© NXP B.V. 2007. All rights reserved.
9-331