PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 715

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
5.5.1 Device Driver Sets Up Descriptors
5.5.2 Rx DMA Manager Reads Rx Descriptor Arrays
5.5.3 Rx DMA Manager Receives Data
After initializing the receive descriptor and status arrays to receive packets from the
Ethernet connection (as defined in
enabled via the MAC1 register and the Control register.
During initialization, each Packet pointer in the descriptors is set to point to a data
fragment buffer. The size of the buffer is stored in the Size bits of the Control field of
the descriptor. Additionally the Control field in the descriptor has an Interrupt bit which
allows generation of an interrupt after a fragment buffer has been filled and its status
has been committed to memory.
After the Receive Datapath is initialized and enabled, all descriptors are owned by the
receive hardware and should not be modified by the software unless hardware hands
over the descriptor by incrementing the RxProduceIndex indicating a packet has been
received. The device driver is allowed to modify the descriptors after a (soft) reset of
the Receive Datapath.
When the RxEnable bit in the Command register is set, the Rx DMA manager reads
descriptors from memory with block transfers at the address determined by
RxDescriptor and RxProduceIndex. The LAN100 will start reading descriptors even
before actual receive data arrives on the MII interface (called descriptor prefetching ).
The block size of the descriptor read block transfer is determined by the total number
of descriptors owned by the hardware: RxConsumeIndex – RxProduceIndex – 1.
Transferring blocks of descriptors maximizes prefetching and minimizes memory
loading. Read data returned from the descriptor read operation is consumed per
descriptor, and only if needed.
After reading the descriptor, the receive DMA engine waits for the MII Interface to
return receive data that pass the receive filtering process. Receive packets that do
not match the filtering criteria are not passed to memory. For more information on
filtering refer to
written in the descriptors fragment buffer in memory. The Rx DMA manager does not
write beyond the size of the buffer. In case a packet is received that is larger than a
descriptor’s fragment buffer, the packet will be written to multiple fragment buffers of
consecutive descriptors. If a multi-fragment packet is received, all but the last
fragment in the packet will return a status word with the Last bit set to 0. Only on the
last fragment of a packet is the Last bit set in the status word. If a fragment buffer is
the last of a packet, the buffer may not be filled completely. The first receive data of
the next packet will be written to the next descriptor’s fragment buffer.
After receiving a fragment, the Rx DMA manager writes status information back to the
StatusInfo and StatusTimeStamp fields of the status word.The LAN100 writes the fill
level of a descriptor’s fragment buffer in the EntryLevel field of the Status word. The
value of the RxProduceIndex is only updated after the fragment data and the
fragment status information has been committed to memory. This is checked by
sensing the write acknowledge signal returned from memory. The Rx DMA manager
continues to receive packets until the descriptor FIFO is full. If it becomes full, the
Section
Rev. 4.0 — 03 December 2007
Chapter 23: LAN100 — Ethernet Media Access Controller
5.12. Once a packet passes the receive filter, the data is
Section
5.3), the Receive Datapath should be
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
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