MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 97

• Manufacturer Part Number: MC68EC020AA25
• Description: IC MPU 32BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020AA25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

5.4.2 Breakpoint Acknowledge Cycle
The breakpoint acknowledge cycle is generated by the execution of a BKPT instruction.
The breakpoint acknowledge cycle allows the external hardware to provide an instruction
word directly into the instruction pipeline as the program executes. This cycle accesses
the CPU space with a type field of zero and provides the breakpoint number specified by
the instruction on address lines A4–A2. If the external hardware terminates the cycle with
DSACK1/DSACK0, the data on the bus (an instruction word) is inserted into the instruction
pipe, replacing the breakpoint opcode, and is executed after the breakpoint acknowledge
cycle completes. The BKPT instruction requires a word to be transferred so that if the first
bus cycle accesses an 8-bit port, a second cycle is required. If the external logic
terminates the breakpoint acknowledge cycle with BERR (i.e., no instruction word
available), the processor takes an illegal instruction exception. Figure 5-35 is a flowchart
of the breakpoint acknowledge cycle. Figure 5-36 shows the timing for a breakpoint
acknowledge cycle that returns an instruction word. Figure 5-37 shows the timing for a
breakpoint acknowledge cycle that signals an exception.
5-50
1) SET R/W TO READ
2) SET FUNCTION CODE TO CPU SPACE
3) PLACE CPU SPACE TYPE 0 ON A19–A16
4) PLACE BREAKPOINT NUMBER ON A4–A2
5) SET SIZE TO WORD
6) ASSERT AS AND DS
IF BERR ASSERTED:
1) PLACE LATCHED DATA IN INSTRUCTION
2) CONTINUE PROCESSING
1) INITIATE ILLEGAL INSTRUCTION PROCESSING
IF DSACK1/DSACK0 ASSERTED:
1) LATCH DATA
2) NEGATE AS AND DS
3) GO TO A
1) NEGATE AS AND DS
2) GO TO B
PIPELINE
BREAKPOINT ACKNOWLEDGE
Figure 5-35. Breakpoint Acknowledge Cycle Flowchart
PROCESSOR
A
M68020 USER’S MANUAL
B
PROCESSING
1) PLACE REPLACEMENT OPCODE ON DATA
2) ASSERT DSACK1/DTACK0
1) ASSERT BERR TO INITIATE EXCEPTION
SLAVE NEGATES DSACK1/DSACK0 OR BERR
BUS
EXTERNAL DEVICE
OR
MOTOROLA