MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 160

IC MPU 32BIT 25MHZ 100-QFP

MC68EC020AA25

Manufacturer Part Number
MC68EC020AA25
Description
IC MPU 32BIT 25MHZ 100-QFP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68EC020AA25

Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
100-QFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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7.2 COPROCESSOR INSTRUCTION TYPES
The M68000 coprocessor interface supports four categories of coprocessor instructions:
general, conditional, context save, and context restore. The category name indicates the
type of operations provided by the coprocessor instructions in the category. The
instruction category also determines the CIR accessed by the MC68020/EC020 to initiate
instruction and communication protocols between the main processor and the
coprocessor necessary for instruction execution.
During the execution of instructions in the general or conditional categories, the
coprocessor uses the set of coprocessor response primitive codes defined for the M68000
coprocessor interface to request services from and indicate status to the main processor.
During the execution of the instructions in the context save and context
MOTOROLA
$0C
$1C
$00
$04
$08
$10
$14
$18
Figure 7-4. Coprocessor Address Map in MC68020/EC020 CPU Space
31
CPU SPACE ADDRESS
Figure 7-5. Coprocessor Interface Register Set Map
OPERATION WORD
REGISTER SELECT
(RESERVED)
$2E01F
$20000
$2001F
$22000
$2201F
$24000
$2E000
RESPONSE
SAVE
M68020 USER’S MANUAL
INTERFACE REGISTER SET
INTERFACE REGISTER SET
INTERFACE REGISTER SET
RESERVED
RESERVED
RESERVED
INSTRUCTION ADDRESS
OPERAND ADDRESS
OPERAND
16
15
ADDRESS SPACE FOR
COPROCESSOR WITH
CpID = 0
ADDRESS SPACE FOR
COPROCESSOR WITH
CpID = 1
ADDRESS SPACE FOR
COPROCESSOR WITH
CpID = 7
(RESERVED)
CONDITION
COMMAND
CONTROL
RESTORE
0
7- 7

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