MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 33

• Manufacturer Part Number: MC68EC020AA25
• Description: IC MPU 32BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020AA25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

on top of the stack was generated by an interrupt, trap, or instruction exception, the RTE
instruction restores the SR and PC to the values saved on the supervisor stack. The
processor then continues execution at the restored PC address and at the privilege level
determined by the S-bit of the restored SR. If the frame on top of the stack was generated
by a bus fault (bus error or address error exception), the RTE instruction restores the
entire saved processor state from the stack.
2.2 ADDRESS SPACE TYPES
The processor specifies a target address space for every bus cycle with the FC2–FC0
signals according to the type of access required. In addition to distinguishing between
supervisor/user and program/data, the processor can identify special processor cycles,
such as the interrupt acknowledge cycle, and the memory management unit can control
accesses and translate addresses appropriately. Table 2-1 lists the types of accesses
defined for the MC68020/EC020 and the corresponding values of the FC2–FC0 signals.
The memory locations of user program and data accesses are not predefined; neither are
the locations of supervisor data space. During reset, the first two long words beginning at
memory location zero in the supervisor program space are used for processor
initialization. No other memory locations are explicitly defined by the MC68020/EC020.
A function code of $7 selects the CPU address space. This is a special address space
that does not contain instructions or operands but is reserved for special processor
functions. The processor uses accesses in this space to communicate with external
devices for special purposes. For example, all M68000 processors use the CPU space for
interrupt acknowledge cycles. The MC68020/EC020 also generate CPU space accesses
for breakpoint acknowledge and coprocessor operations.
Supervisor programs can use the MOVES instruction to access all address spaces,
including the user spaces and the CPU address space. Although the MOVES instruction
can be used to generate CPU space cycles, this may interfere with proper system
operation. Thus, the use of MOVES to access the CPU space should be done with
caution.
2- 4
*
for future use by Motorola.
Address space 3 is reserved for user definition; 0 and 4 are reserved
FC2
0
0
0
0
1
1
1
1
Table 2-1. Address Space Encodings
FC1
0
0
1
1
0
0
1
1
M68020 USER’S MANUAL
FC0
0
1
0
1
0
1
0
1
(Undefined, Reserved)
User Data Space
User Program Space
(Undefined, Reserved)
(Undefined, Reserved)
Supervisor Data Space
Supervisor Program Space
CPU Space
Address Space
*
*
*
MOTOROLA