MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 45

IC MPU 32BIT 25MHZ 100-QFP

MC68EC020AA25

Manufacturer Part Number
MC68EC020AA25
Description
IC MPU 32BIT 25MHZ 100-QFP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68EC020AA25

Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
100-QFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68EC020AA25
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC68EC020AA25
Quantity:
14
Company:
Part Number:
MC68EC020AA25
Quantity:
14
Part Number:
MC68EC020AA25R
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
When an instruction fetch occurs, the cache (if enabled) is first checked to determine if the
word required is in the cache. This check is achieved by first using the index field (A7–A2)
of the access address as an index into the on-chip cache. This index selects one of the 64
entries in the cache. Next, A31–A8 and FC2 are compared to the tag of the selected entry.
(Note that in the MC68EC020, A31–A24 are used for internal on-chip cache tag
comparison.) If there is a match and the valid bit is set, a cache hit occurs. A1 is then used
to select the proper word from the cache entry, and the cycle ends. If there is no match or
if the valid bit is clear, a cache miss occurs, and the instruction is fetched from external
memory. This new instruction is automatically written into the cache entry, and the valid bit
is set unless the F-bit in the CACR is set. Since the processor always prefetches
instructions externally with long-word-aligned bus cycles, both words of the entry will be
updated, regardless of which word caused the miss.
4–2
C
F
2
Data accesses are not cached, regardless of their associated
address space.
F
C
1
Figure 4-1. MC68020/EC020 On-Chip Cache Organization
F
C
0
TAG REPLACE
A
3
1
64 SELECT
1 OF
A
2
3
A
2
2
COMPARATOR
A
2
1
M68020 USER’S MANUAL
A
2
0
TAG
MC68020/EC020 PREFETCH ADDRESS
A
1
9
A
1
8
TAG
A
1
7
LINE
NOTE
HIT
V
A
1
6
VALID
A
1
5
A
1
4
A
1
3
WORD
WORD
A
1
2
ENTRY HIT
A
1
1
A
1
0
SELECT
WORD
A
9
A
8
A
7
A
6
A
5
INDEX
REPLACEMENT
DATA
TO
INSTRUCTION
PATH
CACHE
CONTROL
A
4
A
3
A
2
A
1
MOTOROLA
A
0

Related parts for MC68EC020AA25