MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 221

• Manufacturer Part Number: MC68EC020AA25
• Description: IC MPU 32BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020AA25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Example 3
Both Figures 8-3 and 8-4 show instruction execution without benefit of the
MC68020/EC020 instruction cache. Figure 8-5 shows a third example for the same
instruction stream executing in the cache. Note that once the instructions are in the cache,
the original location in external memory is no longer a factor in timing.
The assumptions for Example 3 are:
Figure 8-5 illustrates the benefits of the instruction cache. The total number of clock cycles
is reduced from 16 to 12 clocks. Since the instructions are resident in the cache, the
instruction prefetch activity does not require the bus controller to perform external bus
cycles. Since prefetch occurs with no delay, the bus controller is idle more often.
Example 4
Idle clock cycles, such as those shown in example 3, are useful in MC68020/EC020
systems that require wait states when accessing external memory. This fact is illustrated
in example 4 (see Figure 8-6) with the following assumptions:
MOTOROLA
1. The data bus is 32 bits,
2. The cache is enabled and instructions are in the cache, and
3. Memory access occurs with no wait states.
1. The data bus is 32 bits,
2. The cache is enabled and instructions are in the cache, and
3. Memory access occurs with one wait state.
EXECUTION TIME
INSTRUCTION
CONTROLLER
SEQUENCER
COUNTER
ACTIVITY
CLOCK
CLOCK
BUS
BUS
Figure 8-5. Processor Activity for Example 3
LEGEND:
1
IDLE
PERFORM
MOVE #1
MOVE.L D4,(A1)+
2
1) MOVE.L D4,(A1)+
2) ADD.L D4,D5
3) MOVE.L (A1),–(A2)
4) ADD.L D5,D6
WRITE TO (A1)+
(4)
WRITE
3
PERFORM
ADD #2
M68020 USER’S MANUAL
4
5
IDLE
CALCULATE
SOURCE EA
MOVE #3
6
READ FROM (A1)
DESTINATION
7
READ
CALCULATE
MOVE.L (A1),–(A2)
MOVE #3
EA
8
(7)
9
PERFORM
MOVE #3
WRITE TO –(A2)
10
WRITE
11
PERFORM
ADD #4
12
ADD.L
D5,D6
IDLE
(1)
13
8- 7