MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 92

• Manufacturer Part Number: MC68EC020AA25
• Description: IC MPU 32BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020AA25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

5.4.1 Interrupt Acknowledge Bus Cycles
When a peripheral device signals the processor (with the IPL2–IPL0 signals) that the
device requires service and when the internally synchronized value on these signals
indicates a higher priority than the interrupt mask in the status register (or that a transition
has occurred in the case of a level 7 interrupt), the processor makes the interrupt a
pending interrupt. Refer to Section 6 Exception Processing for details on the recognition
of interrupts.
The MC68020/EC020 takes an interrupt exception for a pending interrupt within one
instruction boundary (after processing any other pending exception with a higher priority).
The following paragraphs describe the various kinds of interrupt acknowledge bus cycles
that can be executed as part of interrupt exception processing.
5.4.1.1 INTERRUPT ACKNOWLEDGE CYCLE—TERMINATED NORMALLY. When the
MC68020/EC020 processes an interrupt exception, it performs an interrupt acknowledge
cycle to obtain the number of the vector that contains the starting location of the interrupt
service routine.
Some interrupting devices have programmable vector registers that contain the interrupt
vectors for the routines they use. The following paragraphs describe the interrupt
acknowledge cycle for these devices. Other interrupting conditions or devices cannot
supply a vector number and use the autovector cycle described in 5.4.1.2 Autovector
Interrupt Acknowledge Cycle.
MOTOROLA
COMMUNICATION
ACKNOWLEDGE
COPROCESSOR
ACKNOWLEDGE
ACCESS LEVEL
BREAKPOINT
INTERRUPT
CONTROL
FUNCTION
2
Figure 5-31. MC68020/EC020 CPU Space Address Encoding
1 1 1
1 1 1
1 1 1
1 1 1
CODE
0
31
31
31
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
1 1 1
1 1 1
M68020 USER’S MANUAL
1 1 1 1 1 1
24
23
20
20
20
20
ADDRESS BUS
19
19
19
19
CPU SPACE
TYPE FIELD
1 1 1
16
16
16
16
1 1 1
15
15
15
15
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
CpID
13
1 1 1
12
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1
7
6
5
5
4
4
MMU REG
BKPT #
4
3
CP REG
LEVEL
2
1
0 0
1
5- 45
1
0
0
0
0