MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 195

• Manufacturer Part Number: MC68EC020AA25
• Description: IC MPU 32BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020AA25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

The D/A bit specifies whether the primitive transfers an address or data register. D/A = 0
indicates a data register, and D/A = 1 indicates an address register. The register field
contains the register number.
If DR = 0, the main processor writes the long-word operand in the specified register to the
operand CIR. If DR = 1, the main processor reads a long-word operand from the operand
CIR and transfers it to the specified data or address register.
7.4.14 Transfer Main Processor Control Register Primitive
The transfer main processor control register primitive transfers a long-word operand
between one of its control registers and the coprocessor. This primitive applies to general
and conditional category instructions. Figure 7-34 shows the format of the transfer main
processor control register primitive.
The transfer main processor control register primitive uses the CA, PC, and DR bits as
described in 7.4.2 Coprocessor Response Primitive General Format. If the
coprocessor issues this primitive with CA = 0 during a conditional category instruction, the
main processor initiates protocol violation exception processing.
When the main processor receives this primitive, it reads a control register select code
from the register select CIR. This code determines which main processor control register
is transferred. Table 7-5 lists the valid control register select codes. If the control register
select code is not valid, the MC68020/EC020 initiates protocol violation exception
processing (refer to 7.5.2.1 Protocol Violations).
7-42
Figure 7-34. Transfer Main Processor Control Register Primitive Format
15
CA
PC
14
DR
13
12
All other codes cause a protocol violation exception.
0
Select Code
Table 7-5. Main Processor Control
11
1
$x000
$x001
$x002
$x800
$x801
$x802
$x803
$x804
10
1
Register Select Codes
M68020 USER’S MANUAL
9
0
8
1
Control Register
7
0
CACR
CAAR
MSP
SFC
DFC
USP
VBR
ISP
6
0
5
0
4
0
3
0
2
0
1
0
0
MOTOROLA
0