MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 172

• Manufacturer Part Number: MC68EC020AA25
• Description: IC MPU 32BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020AA25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

The information in a coprocessor state frame describes a context of operation for that
coprocessor. This description of a coprocessor context includes the program invisible
state information and, optionally, the program visible state information. The program
invisible state information consists of any internal registers or status information that
cannot be accessed by the program but is necessary for the coprocessor to continue its
operation at the point of suspension. Program visible state information includes the
contents of all registers that appear in the coprocessor programming model and that can
be directly accessed using the coprocessor instruction set. The information saved by the
cpSAVE instruction must include the program invisible state information. If cpGEN
instructions are provided to save the program visible state of the coprocessor, the
cpSAVE and cpRESTORE instructions should only transfer the program invisible state
information to minimize interrupt latency during a save or restore operation.
7.2.3.2 COPROCESSOR FORMAT WORDS. The coprocessor communicates status
information to the main processor during the execution of cpSAVE and cpRESTORE
instructions using coprocessor format words. The format words defined for the M68000
coprocessor interface are listed in Table 7-2.
The upper byte of the coprocessor format word contains the code used to communicate
coprocessor status information to the main processor. The MC68020/EC020 recognizes
four types of format words: empty/reset, not ready, invalid format, and valid format. The
MC68020/EC020 interprets the reserved format codes ($03–$0F) as invalid format words.
The lower byte of the coprocessor format word specifies the size in bytes (which must be
a multiple of four) of the coprocessor state frame. This value is only relevant when the
code byte contains the valid format code (refer to 7.2.3.2.4 Valid Format Word).
7.2.3.2.1 Empty/Reset Format Word. The coprocessor returns the empty/reset format
code during a cpSAVE instruction to indicate that the coprocessor contains no user-
specific information. That is, no coprocessor instructions have been executed since either
a previous cpRESTORE of an empty/reset format code or the previous hardware reset. If
the main processor reads the empty/reset format word from the save CIR during the
initiation of a cpSAVE instruction, it stores the format word at the effective address
specified in the cpSAVE instruction and executes the next instruction.
MOTOROLA
xx—Don’t care
Table 7-2. Coprocessor Format Word Encodings
Format Code
$03–$OF
$10–$FF
$00
$01
$02
Length
M68020 USER’S MANUAL
Length
$xx
$xx
$xx
$xx
Empty/Reset
Not Ready, Come Again
Invalid Format
Undefined, Reserved
Valid Format, Coprocessor Defined
Meaning
7- 19