MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 183

• Manufacturer Part Number: MC68EC020AA25
• Description: IC MPU 32BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020AA25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

The encoding of bits 12–0 of a coprocessor response primitive depends on the individual
primitive. Bits 15–13, however, specify optional additional operations that apply to most of
the primitives defined for the M68000 coprocessor interface.
The CA bit specifies the come-again operation of the main processor. When the main
processor reads a response primitive from the response CIR with the CA bit set, it
performs the service indicated by the primitive and then reads the response CIR again.
Using the CA bit, a coprocessor can transfer several response primitives to the main
processor during the execution of a single coprocessor instruction.
The PC bit specifies the pass program counter operation. When the main processor reads
a primitive with the PC bit set from the response CIR, the main processor immediately
passes the current value in its program counter to the instruction address CIR as the first
operation in servicing the primitive request. The value in the program counter is the
address of the F-line operation word of the coprocessor instruction currently executing.
The PC bit is implemented in all coprocessor response primitives currently defined for the
M68000 coprocessor interface.
When an undefined primitive or a primitive that requests an illegal operation is passed to
the main processor, the main processor initiates exception processing for either an F-line
emulator or a protocol violation exception (refer to 7.5.2 Main-Processor-Detected
Exceptions). If the PC bit is set in one of these response primitives, however, the main
processor passes the program counter to the instruction address CIR before it initiates
exception processing.
When the main processor initiates a cpGEN instruction that can be executed concurrently
with main processor instructions, the PC bit is usually set in the first primitive returned by
the coprocessor. Since the main processor proceeds with instruction stream execution
once the coprocessor releases it, the coprocessor must record the instruction address to
support any possible exception processing related to the instruction. Exception processing
related to concurrent coprocessor instruction execution is discussed in 7.5.1
Coprocessor-Detected Exceptions.
The DR bit is the direction bit. It applies to operand transfers between the main processor
and the coprocessor. If the DR bit is clear, the direction of transfer is from the main
processor to the coprocessor (main processor write). If the DR bit is set, the direction of
transfer is from the coprocessor to the main processor (main processor read). If the
operation indicated by a given response primitive does not involve an explicit operand
transfer, the value of this bit depends on the particular primitive encoding.
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