MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 27

• Manufacturer Part Number: MC68EC020AA25
• Description: IC MPU 32BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020AA25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ASL, ASR
Bcc
BCHG
BCLR
BFCHG
BFCLR
BFEXTS
BFEXTU
BFFFO
BFINS
BFSET
BFTST
BKPT
BRA
BSET
BSR
BTST
CALLM
CAS
CAS2
CHK
CHK2
CLR
CMP
CMPA
CMPI
CMPM
CMP2
DBcc
DIVS, DIVSL
DIVU, DIVUL
EOR
EORI
EXG
EXT, EXTB
ILLEGAL
JMP
JSR
LEA
LINK
LSL, LSR
MOVE
MOVEA
MOVE CCR
MOVE SR
MOTOROLA
Mnemonic
Add Decimal with Extend
Add
Add Address
Add Immediate
Add Quick
Add with Extend
Logical AND
Logical AND Immediate
Branch Conditionally
Test Bit and Change
Test Bit and Clear
Test Bit Field and Change
Test Bit Field and Clear
Signed Bit Field Extract
Unsigned Bit Field Extract
Bit Field Find First One
Bit Field Insert
Test Bit Field and Set
Test Bit Field
Breakpoint
Branch Always
Test Bit and Set
Branch to Subroutine
Test Bit
Call Module
Compare and Swap Operands
Compare and Swap Dual Operands
Check Register Against Bound
Check Register Against Upper and Lower Bound
Clear
Compare
Compare Address
Compare Immediate
Compare Memory to Memory
Compare Register Against Upper and Lower Bounds
Test Condition, Decrement and Branch
Logical Exclusive OR
Logical Exclusive Or Immediate
Exchange Registers
Sign Extend
Jump
Jump to Subroutine
Load Effective Address
Link and Allocate
Logical Shift Left and Right
Move
Move Address
Move Status Register
Arithmetic Shift Left and Right
Signed Divide
Unsigned Divide
Take Illegal Instruction Trap
Move Condition Code Register
Description
Table 1-2. Instruction Set
M68020 USER’S MANUAL
MOVEC
MOVEM
MOVEP
MOVEQ
MOVES
MULU
NBCD
NEG
OR
ORI
ORI CCR
ORI SR
PACK
RESET
ROL, ROR
RTM
STOP
SUB
SUBA
SUBI
SUBX
SWAP
TRAP
TRAPV
UNLK
UNPK
cpBcc
cpDBcc
cpRESTORE
cpScc
cpTRAPcc
MOVE USP
MULS
NEGX
NOP
NOT
PEA
ROXL,ROXR
RTD
RTE
RTR
RTS
SBCD
Scc
SUBQ
TAS
TRAPcc
TST
cpGEN
cpSAVE
Mnemonic
Mnemonic
Move Control Register
Move Multiple Registers
Move Peripheral
Move Quick
Move Alternate Address Space
Unsigned Multiply
Negate Decimal with Extend
Negate
No Operation
Logical Complement
Logical Inclusive OR
Logical Inclusive OR Immediate
Logical Inclusive Or Immediate to Condition Codes
Logical Inclusive OR Immediate to Status Register
Pack BCD
Reset External Devices
Rotate Left and Right
Return from Module
Stop
Subtract
Subtract Address
Subtract with Extend
Swap Register Words
Trap
Trap on Overflow
Unlink
Unpack BCD
Branch Conditionally
Test Coprocessor Condition, Decrement and Branch
Set Conditionally
Trap Conditionally
Signed Multiply
Negate with Extend
Push Effective Address
Rotate with Extend Left and Right
Return and Deallocate
Return from Exception
Return and Restore Codes
Return from Subroutine
Subtract Decimal with Extend
Set Conditionally
Subtract Immediate
Subtract Quick
Test and Set an Operand
Trap Conditionally
Test Operand
Coprocessor General Instruction
Restore Internal State of Coprocessor
Move User Stack Pointer
COPROCESSOR INSTRUCTIONS
Save Internal State of Coprocessor
Description
Description
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