MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 40

• Manufacturer Part Number: MC68EC020AA25
• Description: IC MPU 32BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020AA25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Data Buffer Enable (DBEN, MC68020 only)
Data Transfer and Size Acknowledge (DSACK1, DSACK0)
3.7 INTERRUPT CONTROL SIGNALS
The following signals are the interrupt control signals for the MC68020/EC020. Note that
IPEND is implemented in the MC68020 and not implemented in the MC68EC020.
Interrupt Priority Level Signals (IPL2–IPL0)
Interrupt Pending (IPEND, MC68020 only)
Autovector (AVEC)
MOTOROLA
This output signal is an enable signal for external data buffers. This signal may not be
required in all systems. Refer to Section 5 Bus Operation for more information about
the relationship of DBEN to bus operation.
DBEN is not implemented in the MC68EC020.
These input signals indicate the completion of a requested data transfer operation. In
addition, they indicate the size of the external bus port at the completion of each cycle.
These signals apply only to asynchronous bus cycles. Refer to Section 5 Bus
Operation for more information on these signals and their relationship to dynamic bus
sizing.
These input signals provide an indication of an interrupt condition and the encoding of
the interrupt level from a peripheral or external prioritizing circuitry. IPL2 is the most
significant bit of the level number. For example, since the IPL2–IPL0 signals are active
low, IPL2–IPL0 equal to $5 corresponds to an interrupt request at interrupt level 2.
Refer to Section 6 Exception Processing for information on MC68020/EC020
interrupts.
This output signal indicates that an interrupt request exceeding the current interrupt
priority mask in the SR has been recognized internally. This output is for use by external
devices (coprocessors and other bus masters, for example) to predict processor
operation on the following instruction boundaries. Refer to Section 6 Exception
Processing for interrupt information. Also, refer to Section 5 Bus Operation for bus
information related to interrupts.
IPEND is not implemented in the MC68EC020.
This input signal indicates that the MC68020/EC020 should generate an automatic
vector during an interrupt acknowledge cycle. Refer to Section 5 Bus Operation for
more information about automatic vectors.
M68020 USER’S MANUAL
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