MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 301

• Manufacturer Part Number: MC68EC020AA25
• Description: IC MPU 32BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020AA25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

A1, A0 Signals, 5-2, 5-7, 5-9, 5-21, 9-5
A15–A13 Signals, 7-6
A19–A16 Signals, 7-6
A31–A24 Signals, 4-1, 5-3
AC Specifications, 10-5
Access Level, 9-17
Access Time Calculations, 9-12
Address Bus, 3-2, 5-3, 5-25
Address Error Exception, 5-14, 6-6
Address Registers, 1-4
Address Space, 2-4, 5-3
Addressing Modes, 1-8
Arithmetic/Logical Instruction, 8-30, 8-31
AS Signal, 3-4, 5-2, 5-3
Autovector, 5-48
Autovector Interrupt Acknowledge Cycle, 5-48
AVEC Signal, 3-5, 5-4, 5-48, 5-53
BERR Signal, 3-7, 5-4, 5-25, 5-53, 5-55, 6-4
BG Signal, 3-6, 5-63, 5-66, 5-70
BGACK Signal, 3-6, 5-62, 5-63, 5-66
Binary-Coded Decimal, 8-32
Bit Field Manipulation Instructions, 8-36
Bit Manipulation Instructions, 8-35
BKPT Instruction, 5-50
Block Diagram, 1-2
BR Signal, 3-6, 5-63, 5-66, 5-70, 5-71
Breakpoint Acknowledge Cycle, 5-50, 6-17
Breakpoint Instruction Exception, 6-17
Bus, 5-24
Bus Arbitration (MC68020), 5-63
MOTOROLA
Flowchart, 6-17
Flowchart, 5-50
Timing, 5-50
Arbitration, 5-62
Cycles, 5-1
Master, 5-1
Operation, 5-1, 5-24
— A —
— B —
M68020 USER’S MANUAL
INDEX
Bus Arbitration (MC68EC020), 5-70
Bus Controller, 5-22, 8-2, 8-5
Bus Cycles, 5-1, 5-25
Bus Error Exception, 6-4, 6-21
Bus Fault, 6-21
Bus Master, 5-1, 5-25, 5-62
Bus Operation, 5-24
Byte Enable Signals, 5-21
Byte Select Control Signals, 9-5
Cache, 1-13, 4-1, 5-2, 5-22, 5-62, 8-1, 8-7, 9-11
Cache Address Register (CAAR), 1-7, 4-3, 4-4
Cache Control Register (CACR), 1-7, 4-2, 4-3
CALLM Instruction, 9-14, 9-16, 9-18
CAS Instruction, 5-39
CAS2 Instruction, 5-39
CDIS Signal, 3-7, 4-3
CLK Signal, 3-7
Clock Drivers, 9-10
Condition Codes, 1-7
Conditional Branch Instructions, 8-37
Control Instructions, 8-38
Coprocessor, 6-25, 7-1
Control Unit, 5-67
Flowchart, 5-63
Read-Modify-Write, 5-68
Timing, 5-63
Control Unit, 5-73
Flowchart, 5-70
Timing, 5-70
Two-Wire, 5-75, A-1
Control, 4-3
Internal Cache Holding Register, 5-21
Reset, 4-3
Classification, 7-4
Communication Protocol, 7-4
Conditional Instruction Category, 7-10
Coprocessor Context Restore Instruction
Category, 7-22
— C —
INDEX-1