MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 216

• Manufacturer Part Number: MC68EC020AA25
• Description: IC MPU 32BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020AA25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

When prefetching instructions from external memory, the microprocessor will utilize long-
word read cycles. When the read is aligned on a long-word address boundary, the
processor reads two words, which may load two instructions at once or two words of a
multiword instruction. The subsequent instruction prefetch will find the second word is
already available, and there is no need to run an external bus cycle (read).
The MC68020/EC020 always prefetches long words. When an instruction prefetch falls on
an odd-word boundary (e.g., due to a branch to an odd-word location), the
MC68020/EC020 will read the even word associated with the long-word base address at
the same time as (32-bit memory) or before (8- or 16-bit memory) the odd word is read.
When an instruction prefetch falls on an even-word boundary (as would be the normal
case), the MC68020/EC020 reads both words at the long-word address, thus effectively
prefetching the next two words.
8.1.2 Operand Misalignment
Another significant factor affecting instruction timing is operand misalignment. Operand
misalignment has impact on performance when the microprocessor is reading or writing
external memory. In this case, the address of a word operand falls across a long-word
boundary, or a long-word operand falls on a byte or word address that is not a long-word
boundary. Although the MC68020/EC020 will automatically handle all occurrences of
operand misalignment, it must use multiple bus cycles to complete such transfers.
8.1.3 Bus/Sequencer Concurrency
The bus controller is responsible for all bus activity. The sequencer controls the bus
controller, instruction execution, and internal processor operation, such as calculation of
effective addresses and setting of condition codes.
The bus controller and sequencer can operate on an instruction concurrently. The bus
controller can perform a read or write while the sequencer controls an effective address
calculation or sets the condition codes. The sequencer may also request a bus cycle that
the bus controller cannot immediately perform. In this case, the bus cycle is queued and
the bus controller runs the cycle when the current cycle is complete.
8-2
M68020 USER’S MANUAL
MOTOROLA