Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 98

DEV KIT FOR Z16F ZNEO

Z16F2800100ZCOG

Manufacturer Part Number
Z16F2800100ZCOG
Description
DEV KIT FOR Z16F ZNEO
Manufacturer
Zilog
Series
ZNEO™r
Type
MCUr

Specifications of Z16F2800100ZCOG

Contents
Evaluation Board, Software and Documentation
For Use With/related Products
Z16F Series
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4537
Architecture
Operation
PS022008-0810
Master Interrupt Enable
Figure 18
The master interrupt enable bit in the flag register globally enables or disables interrupts.
This bit has been moved to the flag register (bit-0). Thus, anytime the register is loaded, it
changes the state of the IRQE bit. For the
been pushed on the stack.
Interrupts are globally enabled by any of the following actions:
Interrupts are globally disabled by any of the following actions:
Internal Interrupts
Port Interrupts
controller
Execution of an Enable Interrupt (
Writing 1 to the IRQE bit in the flag register
Execution of a Disable Interrupt (
ZNEO CPU acknowledgement of an interrupt service request from the interrupt
Writing 0 to the IRQE bit in the flag register
displays a block diagram of the interrupt controller.
Figure 18. Interrupt Controller Block Diagram
P R E L I M I N A R Y
DI
EI
Medium
Priority
Priority
Priority
High
Low
) instruction
) instruction
IRET
instruction the bit is set based on what has
Priority
Mux
Vector
Product Specification
IRQ Request
ZNEO
Interrupt Controller
Z16F Series
83

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