Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 121

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

Table 56. Timer 0-2 High Byte Register (TxH)
Timer Control Register Definitions
BITS
FIELD
RESET
R/W
ADDR
PS022008-0810
Reading Timer Count Values
Timer 0-2 High and Low Byte Registers
7
The current count value in the timer is read while counting (enabled). This has no effect on
timer operation. Normally, the count must be read with one 16-bit operation. However, 
8 bit reads are done with the following method. When the timer is enabled and the timer
high byte register is read, the contents of the timer low byte register are placed in a holding
register. A subsequent read from the timer low byte register returns the value in the
holding register. This operation allows accurate reads of the full 16-bit timer count value
when enabled. When the timer is not enabled, a read from the timer low byte register
returns the actual value in the counter.
The Timers can be cascaded by using the Cascade bit in the Timer control registers. When
this bit is set for a Timer, the input source is redefined. When the Cascade bit is set for
Timer0, the input for Timer0 is the output of the Analog Comparator. When the Cascade
bit is set for Timer1 and Timer2, the output of Timer0 and Timer1 become the input for
Timer1 and Timer2, respectively. Any Timer Mode can be used. Timer0 can be cascaded
to Timer1 only by setting the Cascade bit for Timer1. Timer1 cascaded to Timer2 only by
setting the Cascade bit for Timer2. Or all three cascaded, Timer0 to Timer1 or Timer2 for
really long counts by setting the Cascade bit for Timer1 and Timer2.
The Timer 0-2 high and low byte (TxH and TxL) registers (see
contain the current 16-bit timer count value. When the timer is enabled, a read from TxH
stores the value in TxL to a temporary holding register. A read from TxL always returns
this temporary register when the timer is enabled. When the timer is disabled, reads from
the TxL reads the register directly.
Writing to the timer high and low byte registers while the timer is enabled is not
recommended. There are no temporary holding registers available for Write operations, so
simultaneous 16-bit writes are not possible. When either of the timer high or low byte
registers are written during counting, the 8-bit written value is placed in the counter (High
or Low Byte) at the next clock edge. The counter continues counting from the new value.
6
5
FF-E300H, FF-E310H, FF-E320H
P R E L I M I N A R Y
4
R/W
00H
TH
3
2
Table 56
Product Specification
ZNEO
1
and
Z16F Series
Table
57)
Timers
0
106