Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 250
Z16F2800100ZCOG
Manufacturer Part Number
Z16F2800100ZCOG
Description
DEV KIT FOR Z16F ZNEO
Manufacturer
Zilog
Series
ZNEO™r
Type
MCUr
Datasheets
1.Z16F2800100ZCOG.pdf
(2 pages)
2.Z16F2800100ZCOG.pdf
(30 pages)
3.Z16F2800100ZCOG.pdf
(388 pages)
Specifications of Z16F2800100ZCOG
Contents
Evaluation Board, Software and Documentation
For Use With/related Products
Z16F Series
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4537
- Current page: 250 of 388
- Download datasheet (22Mb)
Table 117. I
Table 116. I2CSTATE_L
BITS
FIELD
RESET
R/W
ADDR
PS022008-0810
State
I2CSTATE_H
0000–0100
0110–0111
0101
1000–1111
I
2
C Mode Register
DMAIF
2
C Mode Register (I2CMODE)
R/W
7
0
Sub-State
I2CSTATE_L
0000
0000
0000
0001
0111
0110
0101
0100
0011
0010
0001
0000
1000
The I
operating mode, Slave address and diagnostic modes.
2
C Mode register (see
6
MODE[1:0]
Sub-state Name
—
—
Master Start
Master Restart
send/receive bit 7
send/receive bit 6
send/receive bit 5
send/receive bit 4
send/receive bit 3
send/receive bit 2
send/receive bit 1
send/receive bit 0
send/receive
Acknowledge
R/W
0
5
P R E L I M I N A R Y
Table
R/W
117) provides control over Master versus Slave
IRM
4
0
FF-E246H
State Description
There are no substates for these I2CSTATE_H
values.
There are no substates for these I2CSTATE_H
values.
Initiating a new transaction.
new one without letting the bus go non-active.
Sending/Receiving most significant bit.
Sending/Receiving least significant bit
Sending/Receiving Acknowledge
Master is ending one transaction and starting a
GCE
R/W
3
0
2
SLA[9:8]
I
2
R/W
C Master/Slave Controller
Product Specification
0
ZNEO
1
Z16F Series
DIAG
R/W
0
0
234
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