Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 235

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

s
PS022008-0810
Figure 48. Data Transfer Format - Slave Receive Transaction with 10-Bit Address
3. Software responds to the interrupt by reading the I2CISTAT register (which clears the
4. The Master detects the acknowledge and sends the byte of data.
5. The I
6. Software responds by reading the I2CISTAT register, finding the
7. The Master and Slave loop on steps 4–6 until the Master detects a Not Acknowledge
8. The Master sends the STOP or RESTART signal on the bus. Either of these signals
Slave Receive Transaction with 10-Bit Address
The data transfer format for writing data from Master to Slave with 10-bit addressing is
shown in
operating as a Slave in 10-bit addressing mode, receiving data from the bus Master.
1. Software configures the controller for operation as a Slave in 10-bit addressing mode
S
– Initialize the MODE field in the I2CMODE register for either SLAVE-ONLY mode
– Optionally set the
– Initialize the
– Set
– Program the Baud Rate High and Low Byte registers for the I
SAM
0, no immediate action is required until the first byte of data is received. If software is
only able to accept a single byte it sets the
Acknowledge depending on the state of the
controller generates the receive data interrupt by setting the
register.
reading the I2CDATA register clearing the
more data byte, it sets the
instruction or runs out of data to send.
cause the I
register). When the Slave receive data from the Master, software takes no action in
response to the Stop interrupt other than reading the I2CISTAT register, clearing the
STOP bit in the I2CISTAT register.
as follows.
Slave Address
or MASTER/SLAVE mode with 10-bit addressing.
I2CMODE register.
1st Byte
bit). After verifying that the
2
Figure
IEN
C controller receives the data byte and responds with Acknowledge or Not
2
= 1 in the I2CCTL register. Set
C Controller to assert the Stop interrupt (STOP bit = 1 in the I2CISTAT
48. The following procedure describes the I
SLA
W=0 A Slave Address
[7:0] bits in the I2CSLVAD register and the
GCE
P R E L I M I N A R Y
bit.
NAK
2nd Byte
bit in the I2CCTL register.
SAM
bit = 1, software checks the
NAK
NAK
RDRF
A
NAK
= 0 in the I
bit in the I2CCTL register at this time.
bit in the I2CCTL register. The I
Data
bit. If software accepts only one
2
C Master/Slave Controller
A
2
I
2
C Control register.
RDRF
C Master/Slave Controller
Product Specification
ZNEO
SLA
2
Data
C baud rate.
RDRF
bit in the I2CISTAT
RD
[9:8] bits in the
bit. When
bit=1 and
Z16F Series
A/A
RD
P/S
2
C
=
219