Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 198

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

PS022008-0810
Input Sample Time
Modes of Operation
(CLKPOL = 0)
(CLKPOL = 1)
This section describes the different modes of data transfer supported by the ESPI block.
The mode is selected by the slave select mode (SSMD) field of the mode register.
SPI Mode
This mode is selected by setting the SSMD field of the mode Register to 000. In this
mode, software or DMA controls the assertion of the SS signal directly via the SSV bit of
the SPI transmit data command register. Either DMA or software is used to control an SPI
mode transaction. Prior to or simultaneously with writing the first transmit data byte,
software or DMA sets the SSV bit. Software sets the SSV bit either by performing a byte
write to the transmit data command register prior to writing the first transmit character to
the data register or by performing a word write to the data register address which loads the
first transmit character and simultaneously sets the SSV bit.
The DMA sets the SSV bit via the command field of the descriptor. The SSV bit is written
on the DMA command bus prior to or in sync with the first data byte. SS will remain
asserted while one or more characters are transferred. There are two mechanisms for
deasserting SS at the end of the transaction. One method is used by DMA and also by
MOSI
MISO
SCK
SCK
SS
Figure 36. ESPI Timing when
Bit7
Bit7
Bit6
Bit6
P R E L I M I N A R Y
Bit5
Bit5
Bit4
Bit4
PHASE
Bit3
Bit3
Enhanced Serial Peripheral Interface
= 1
Bit2
Bit2
Product Specification
ZNEO
Bit1
Bit1
Bit0
Bit0
Z16F Series
182