Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 297

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

Table 144. DMA Select Register (DAMxREQSEL)
PS022008-0810
BITS
FIELD
RESET
R/W
ADDR
DMA Interrupts
DMA Request Select Register
R
7
0
DMA Bandwidth Selection
In the CPUCTL register, the DMABW mode bits set the maximum bus bandwidth the
DMA is allowed. There are four modes (For more details, refer to the ZNEO CPU User
Manual (UM0188)).
Table 143. DMA Bandwidth Selection
Each DMA has its own interrupt vector. For additional information on the interrupts, see
the interrupt section.
Interrupts occur on the following conditions:
•
•
•
CHANSTATE—Channel State 
0000 = DMA Off
0001 = Direct Mode, Waiting for End of Frame signal
Bits
00
01
10
11
Whenever a buffer is completed which has its IEOB set.
When the upper eight bits of the transfer length equal zero and the lower eight bits of
If a buffer has been terminated by a Request EOF.
the transfer length is equal to the DMAxLAR[23:16] and the DMA is in direct mode.
R
6
CHANSTATE
0
Description
DMA uses 100% of the bandwidth
DMA is allowed one transfer for each CPU operation
DMA is allowed one transfer for every two CPU operations
DMA is allowed one transfer for every three CPU
operations
FFE400H, FFE401H, FFE402H, FFE403H
Table 143
R
5
0
P R E L I M I N A R Y
lists the DMA bandwidth selection.
R
4
0
R/W
3
0
R/W
2
0
REQSEL
Product Specification
ZNEO
R/W
1
0
DMA Controller
Z16F Series
R/W
0
0
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