Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 125
Z16F2800100ZCOG
Manufacturer Part Number
Z16F2800100ZCOG
Description
DEV KIT FOR Z16F ZNEO
Manufacturer
Zilog
Series
ZNEO™r
Type
MCUr
Datasheets
1.Z16F2800100ZCOG.pdf
(2 pages)
2.Z16F2800100ZCOG.pdf
(30 pages)
3.Z16F2800100ZCOG.pdf
(388 pages)
Specifications of Z16F2800100ZCOG
Contents
Evaluation Board, Software and Documentation
For Use With/related Products
Z16F Series
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4537
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- Download datasheet (22Mb)
Table 63. Timer 0-2 Control 1 Register (TxCTL1)
BITS
FIELD
RESET
R/W
ADDR
PS022008-0810
Bit Position
[3:1]
PWMD
[0]
INCAP
Bit Position
[7]
TEN
TEN
R/W
7
0
Timer 0-2 Control 1 Register
The Timer 0-2 control 1 (TxCTL1) register enables/disables the timer, sets the prescaler
value, and determines the timer operating mode.
Value (H) Description
Value (H) Description
000
001
010
100
101
011
110
111
0
1
0
1
TPOL
R/W
6
0
PWM Delay Value
This field is a programmable delay to control the number of additional system
clock cycles following a PWM or Reload compare before the timer output or
the timer output complement is switched to the active state. This field ensures
a time gap between deassertion of o ne PWM outpu t to the assertion of its
complement.
No delay.
2 cycles delay.
4 cycles delay.
8 cycles delay.
16 cycles delay.
32 cycles delay.
64 cycles delay.
128 cycles delay.
Input Capture Event
Previous timer interrupt is not a result of a timer input capture event.
Previous timer interrupt is a result of a timer input capture event.
Timer is disabled.
Timer is enabled.
Note: TEN bit is cleared automatically when the timer stops.
5
FF-E307H, FF-E317H, FF-E327H
P R E L I M I N A R Y
PRES
R/W
000
4
3
2
Product Specification
ZNEO
TMODE
R/W
000
1
Z16F Series
Timers
0
110
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