Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 367
Z16F2800100ZCOG
Manufacturer Part Number
Z16F2800100ZCOG
Description
DEV KIT FOR Z16F ZNEO
Manufacturer
Zilog
Series
ZNEO™r
Type
MCUr
Datasheets
1.Z16F2800100ZCOG.pdf
(2 pages)
2.Z16F2800100ZCOG.pdf
(30 pages)
3.Z16F2800100ZCOG.pdf
(388 pages)
Specifications of Z16F2800100ZCOG
Contents
Evaluation Board, Software and Documentation
For Use With/related Products
Z16F Series
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4537
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Table 194. SPI Master Mode Timing
PS022008-0810
Parameter
SPI Master
T
T
T
1
2
3
(Output)
(Input)
MOSI
MISO
SCK
SPI Master Mode Timing
Figure 76
shown with SCK rising edge used to source MOSI output data, SCK falling edge used to
sample MISO input data. Timing on the SS output pin(s) is controlled by software.
Abbreviation
SCK Rise to MOSI output Valid Delay
MISO input to SCK (receive edge) Setup Time
MISO input to SCK (receive edge) Hold Time
T1
and
Table 194
Figure 76. SPI Master Mode Timing
provides timing information for SPI Master mode pins. Timing is
P R E L I M I N A R Y
T2
Input Data
T3
Output Data
Min
–5
20
0
Delay (ns)
Product Specification
Electrical Characteristics
ZNEO
Max
+5
Z16F Series
351
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