Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 371

DEV KIT FOR Z16F ZNEO

Z16F2800100ZCOG

Manufacturer Part Number
Z16F2800100ZCOG
Description
DEV KIT FOR Z16F ZNEO
Manufacturer
Zilog
Series
ZNEO™r
Type
MCUr

Specifications of Z16F2800100ZCOG

Contents
Evaluation Board, Software and Documentation
For Use With/related Products
Z16F Series
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4537
Table 198. UART Timing without CTS
PS022008-0810
Parameter Abbreviation
T
T
1
2
(Output)
(Output)
DE
TXD
DE Assertion to TXD Falling Edge (Start)
Delay
End of Stop Bit(s) to DE Deassertion Delay
Figure 80
the Clear To Send input signal (CTS) is not used for flow control. In this example, it is
assumed that the Driver Enable polarity has been configured to be Active Low and is 
represented here by DE. DE asserts after the UART Transmit Data register has been 
written. DE remains asserted for multiple characters as long as the Transmit Data register
is written with the next character before the current character has completed.
and
Table 198
T
Figure 80. UART Timing without CTS
1
Start
provide timing information for UART pins for the case where
P R E L I M I N A R Y
Bit 0
Bit 1
1 * XIN period
1 Bit period
Min
Delay (ns)
Bit 7
Product Specification
Parity
2 * XIN period
1 Bit period +
1 * XIN period
Electrical Characteristics
ZNEO
Max
Stop
Stop Bit(s)
End of
Z16F Series
T
2
355

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