Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 191
Z16F2800100ZCOG
Manufacturer Part Number
Z16F2800100ZCOG
Description
DEV KIT FOR Z16F ZNEO
Manufacturer
Zilog
Series
ZNEO™r
Type
MCUr
Datasheets
1.Z16F2800100ZCOG.pdf
(2 pages)
2.Z16F2800100ZCOG.pdf
(30 pages)
3.Z16F2800100ZCOG.pdf
(388 pages)
Specifications of Z16F2800100ZCOG
Contents
Evaluation Board, Software and Documentation
For Use With/related Products
Z16F Series
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4537
- Current page: 191 of 388
- Download datasheet (22Mb)
Enhanced Serial Peripheral Interface
Architecture
PS022008-0810
The Enhanced Serial Peripheral Interface (ESPI) supports SPI (Serial Peripheral Interface)
and Inter IC Sound (I
The features of the ESPI include:
•
•
•
•
•
•
•
The ESPI is a full-duplex, synchronous, character-oriented channel that supporting a
four-wire interface (serial clock, transmit and receive data, and Slave select). The ESPI
block consists of a shift register, transmit and receive data buffer registers, a baud rate
(clock) generator, control/status registers, and a control state machine. Transmit and
receive transfers are in sync as there is a single shift register for both transmit and receive
data.
Full-duplex, synchronous, character-oriented communication.
Four-wire interface (SS, SCK, MOSI, MISO).
Transmit and receive buffer registers to enable high throughput.
Transfer rates up to maximum of one-fourth the system clock frequency. This is in
SLAVE mode.
Error detection.
Dedicated programmable baud rate generator (BRG).
Data transfer control through polling, interrupt, or DMA.
Figure 34
on page 176 displays a block diagram of the ESPI.
2
S) modes of operation.
P R E L I M I N A R Y
Enhanced Serial Peripheral Interface
Product Specification
ZNEO
Z16F Series
175
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