AD9915 AD [Analog Devices], AD9915 Datasheet - Page 6

• Manufacturer Part Number: AD9915
• Description: 2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC
• Manufacturer: AD [Analog Devices]

Parameter
PARALLEL PORT TIMING
SERIAL PORT TIMING
DATA PORT TIMING
DATA LATENCY (PIPELINE DELAY)
AD9915
Write Timing
Read Timing
CS
D[31:0] Setup Time to SYNC_CLK
D[31:0] Hold Time to SYNC_CLK
F[3:0] Setup Time to SYNC_CLK
F[3:0] Hold Time to SYNC_CLK
IO_UPDATE Pin Setup Time to
IO_UPDATE Pin Hold Time to
Profile Pin Setup Time to SYNC_CLK
Profile Pin Hold Time to SYNC_CLK
DR_CTL/DR_HOLD Setup Time to
DR_CTL/DR_HOLD Hold Time to
SCLK Clock Rate (1/t
SCLK Pulse Width High, t
SCLK Pulse Width Low, t
SDIO to SCLK Setup Time, t
SDIO to SCLK Hold Time, t
SCLK Falling Edge to Valid Data on
CS
CS
Single Tone Mode (Matched Latency
Single Tone Mode (Matched Latency
Address Setup Time to
Address Hold Time to
Data Setup Time to
Data Hold Time to
WR
WR
Minimum
Address to Data Valid
Address Hold to
RD
RD
RD
RD
SYNC_CLK
SYNC_CLK
SYNC_CLK
SYNC_CLK
Disabled)
Frequency
Phase
Amplitude
Enabled)
Frequency
Phase
Amplitude
SDIO/SDO, t
to SCLK Setup Time, t
to SCLK Hold Time, t
Minimum Pulse Width High, t
Active to Data Valid
Inactive to Data Tristate
Minimum Low Time
Minimum High Time
Minimum Low Time
Minimum High Time
WR
DV
Time
RD
CLK
WR
WR
Inactive
)
H
LOW
WR
S
HIGH
Inactive
WR
DH
Inactive
DS
Inactive
Active
PWH
Min
1
3.8
1.5
5.1
4.9
4
4
2
2
2
2
2
Typ
320
296
104
320
320
320
Rev. A | Page 6 of 48
Max
0
0
2.1
3.8
10.5
92
0
69
50
69
50
80
0
78
0
0
0
0
0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
Test Conditions/Comments
SCLK duty cycle = 50%
SYSCLK cycles = f
in GHz
S
= system clock frequency
Data Sheet