AD9915 AD [Analog Devices], AD9915 Datasheet - Page 17

• Manufacturer Part Number: AD9915
• Description: 2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC
• Manufacturer: AD [Analog Devices]

Data Sheet
THEORY OF OPERATION
The
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The modes define the data source used to supply the DDS with
its signal control parameters: frequency, phase, or amplitude.
The partitioning of the data into different combinations
of frequency, phase, and amplitude is established based on the
mode and/or specific control bits and function pins.
Although the various modes are described independently, they
can be enabled simultaneously. This provides an unprecedented
level of flexibility for generating complex modulation schemes.
However, to avoid multiple data sources from driving the same
DDS signal control parameter, the device has a built-in priority
protocol.
In single tone mode, the DDS signal control parameters come
directly from the profile programming registers. In digital ramp
modulation mode, the DDS signal control parameters are
delivered by a digital ramp generator. In parallel data port
modulation mode, the DDS signal control parameters are driven
directly into the parallel port.
The various modulation modes generally operate on only one of
the DDS signal control parameters (two in the case of the polar
modulation format via the parallel data port). The unmodulated
DDS signal control parameters are stored in programming
registers and automatically routed to the DDS based on the
selected mode.
A separate output shift keying (OSK) function is also available.
This function employs a separate digital linear ramp generator
that affects only the amplitude parameter of the DDS. The OSK
function has priority over the other data sources that can drive
the DDS amplitude parameter. As such, no other data source
can drive the DDS amplitude when the OSK function is enabled.
SINGLE TONE MODE
In single tone mode, the DDS signal control parameters are
supplied directly from the profile programming registers. A
profile is an independent register that contains the DDS signal
control parameters. Eight profile registers are available. Note
that the profile pins must be used to select the desired register.
PROFILE MODULATION MODE
Each profile is independently accessible. For FSK, PSK, or ASK
modulation, use the three external profile pins (PS[2:0]) to
select the desired profile. A change in the state of the profile
pins with the next rising edge on SYNC_CLK updates the DDS
with the parameters specified by the selected profile. Therefore,
AD9915
Single tone
Profile modulation
Digital ramp modulation (linear sweep)
Parallel data port modulation
Programmable modulus mode
has five modes of operation.
Rev. A | Page 17 of 48
the profile change must meet the setup and hold times to the
SYNC_CLK rising edge. Note that amplitude control must also
be enabled using the OSK enable bit in the CFR1 register
(0x00[8]).
DIGITAL RAMP MODULATION MODE
In digital ramp modulation mode, the modulated DDS signal
control parameter is supplied directly from the digital ramp
generator (DRG). The ramp generation parameters are
controlled through the serial or parallel I/O port.
The ramp generation parameters allow the user to control both
the rising and falling slopes of the ramp. The upper and lower
boundaries of the ramp, the step size and step rate of the rising
portion of the ramp, and the step size and step rate of the falling
portion of the ramp are all programmable.
The ramp is digitally generated with 32-bit output resolution.
The 32-bit output of the DRG can be programmed to affect
frequency, phase, or amplitude. When programmed for frequency,
all 32 bits are used. However, when programmed for phase or
amplitude, only the 16 MSBs or 12 MSBs, respectively, are used.
The ramp direction (rising or falling) is externally controlled by
the DRCTL pin. An additional pin (DRHOLD) allows the user
to suspend the ramp generator in its present state. Note that
amplitude control must also be enabled using the OSK enable
bit in Register CFR1.
PARALLEL DATA PORT MODULATION MODE
In parallel data port modulation mode, the modulated DDS
signal control parameter(s) are supplied directly from the 32-bit
parallel data port. The function pins define how the 32-bit data-
word is applied to the DDS signal control parameters. Format-
ting of the 32-bit data-word is unsigned binary, regardless of the
destination.
Parallel Data Clock (SYNC_CLK)
The
that runs at 1/16 of the DAC sample rate (the sample rate of the
parallel data port). SYNC_CLK serves as a data clock for the
parallel port.
PROGRAMMABLE MODULUS MODE
In programmable modulus mode, the DRG is used as an
auxiliary accumulator to alter the frequency equation of the
DDS core, making it possible to implement fractions that are
not restricted to a power of 2 in the denominator. A standard
DDS is restricted to powers of 2 as a denominator because the
phase accumulator is a set of bits as wide as the frequency
tuning word (FTW).
When in programmable modulus mode, however, the
frequency equation is:
where f
AD9915
f
0
= (f
0
/f
S
S
< ½, 0 ≤ FTW < 2
)(FTW + A/B)/2
generates a clock signal on the SYNC_CLK pin
32
31
, 2 ≤ B ≤ 2
32
– 1, and A < B.
AD9915